1. טכניון – מכון טכנולוגי לישראל הפקולטה להנדסת חשמל PowerPC based reliable computer Students:Guy Derry Gil Wiechman Instructor: Isaschar Walter Winter 2003 Students:Guy Derry Gil Wiechman Instructor: Isaschar Walter Winter 2003 Characterization presentation

2. Problem: In space, VLSI devices are exposed to large amounts of cosmic radiation, since there is no atmosphere to filter it out. Therefore, the MTBF of electronic equipment in space is greatly reduced. Problem: In space, VLSI devices are exposed to large amounts of cosmic radiation, since there is no atmosphere to filter it out. Therefore, the MTBF of electronic equipment in space is greatly reduced. Solution: Design of redundant devices to be used in space systems, hence increasing overall system reliability. Solution: Design of redundant devices to be used in space systems, hence increasing overall system reliability.

3. Project goals Develop a working prototype of a satellite computer, implementing the peripheral device monitoring and operation algorithm. Examine policies of managing redundant peripherals and select one. Implement the chosen algorithm on the Virtex II Pro FPGA board

4. Project Assumptions In this project, we assume correct operation of the software, on a correctly operating single processor. In this project, we assume correct operation of the software, on a correctly operating single processor. The issue of multiple processors handling is examined under a different project, running concurrently to ours. The issue of multiple processors handling is examined under a different project, running concurrently to ours.

5. General block diagram Xilinx Virtex-II Pro FPGA Xilinx Virtex-II Pro FPGA On-Board Peripherals On-Board Peripherals Off-Board Peripherals interface Off-Board Peripherals interface

6. Monitor PPC405 General block diagram P1P2P3P1P2P3 Monitor M1M2M3M1M2M3 Memory-fault Monitor Memory-fault Monitor LUT 101001001010010010100 101001010101010100111 111010100101010101010 100100100101010101101 010101010011011011010 101011011010001001010 010101010110101010101 011010101010010010100 001010100100101101010 100101011011010101010 110110110100011011101 101010100100100111111 LUT 101001001010010010100 101001010101010100111 111010100101010101010 100100100101010101101 010101010011011011010 101011011010001001010 010101010110101010101 011010101010010010100 001010100100101101010 100101011011010101010 110110110100011011101 101010100100100111111 LUT 101001001010010010100 101001010101010100111 111010100101010101010 100100100101010101101 010101010011011011010 101011011010001001010 010101010110101010101 011010101010010010100 001010100100101101010 100101011011010101010 110110110100011011101 101010100100100111111 LUT 101001001010010010100 101001010101010100111 111010100101010101010 100100100101010101101 010101010011011011010 101011011010001001010 010101010110101010101 011010101010010010100 001010100100101101010 100101011011010101010 110110110100011011101 101010100100100111111 LUT 010010010100100101010 101001010101010100111 111010100101010101010 100100100101010101101 010101010011011011010 101011011010001001010 010101010110101010101 011010101010010010100 001010100100101101010 100101011011010101010 110110110100011011101 101010100100100111111 LUT 010010010100100101010 101001010101010100111 111010100101010101010 100100100101010101101 010101010011011011010 101011011010001001010 010101010110101010101 011010101010010010100 001010100100101101010 100101011011010101010 110110110100011011101 101010100100100111111

7. S/W & H/W Requirements Xilinx Virtex-II Pro mounted on evaluation board incl. Serial / USB / Other ports Software running on RT OS (Wind River) which communicates with connected peripherals and implements a monitoring & fault tolerant operation algorithm

8. Project schedule – Qtr. I Wk. I: Wk. III: Wk. IV: Study the PPC405 Processor core Study the PPC405 Processor core Study the Virtex-II Pro component design Study the Virtex-II Pro component design Get familiar with VHDL development environment Get familiar with VHDL development environment Write a “Hello, world!” program for the Virtex-II Pro Write a “Hello, world!” program for the Virtex-II Pro Wk. II:

9. Project schedule – Qtr. I (cont.) Wk. V: Wk. VI: Wk. VII: Expand programming abilities; study & work with peripheral interface Expand programming abilities; study & work with peripheral interface Continue working on FPGA / Study the monitoring algorithm 1 Continue working on FPGA / Study the monitoring algorithm 1 Continue working on FPGA / Begin implementing the monitoring algorithm Continue working on FPGA / Begin implementing the monitoring algorithm 1 Depending on component availability

10. Project schedule - First Semester Goals Full operation of all units (on & off board), incl. unit disconnection ability Full operation of all units (on & off board), incl. unit disconnection ability Multiple peripheral unit operation ability Multiple peripheral unit operation ability Fault tolerant memory access Fault tolerant memory access

11. Project schedule - Second Semester Goals Most of the work on redundancy will be performed during the second semester Most of the work on redundancy will be performed during the second semester Final goal: fully operative system incl. a simulation of an identification and correct operation in case of a faulty device Final goal: fully operative system incl. a simulation of an identification and correct operation in case of a faulty device