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SCT Week -CERN- September 23, 2003 1 Defective ASIC’s A. Ciocio - LBNL.

Published byGrant Miller Modified over 8 years ago

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Presentation on theme: "SCT Week -CERN- September 23, 2003 1 Defective ASIC’s A. Ciocio - LBNL."— Presentation transcript:

1 SCT Week -CERN- September 23, 2003 1 Defective ASIC’s A. Ciocio - LBNL

2 SCT Week -CERN- September 23, 2003 2 List of Defective ASIC’s 2022004020001111Z40859-W11LGSReplaced 202200402000136Z40859-W02 MechanicalReplaced 202200402000201Z40859-W014TokenReplaced 202200402000218Z40859-W09LGSReplaced 202200402000217Z40859-W09BlockLGHOLD 2022004020002210Z40859-W09LowGto rework 202200402000359Z40859-W01MechanicalReplaced 202200402000356Z40859-W01TimeWalkReplaced 2022004020003910Z40859-W04MechanicalReplaced 202200402000392Z40859-W04LGSok to use 202200402000396Z40859-W04LGSok to use 202200402000412Z40802-W09LGSok to use 202200402000469Z40803-W02LGSok to use 202200402000470Z40862-W11NegOffto rework 202200402000486Z40803-W02AbnCalok to use 202200402000489Z40803-W02LGSok to use 2022004020005010Z40862-W11TimeWalkto rework 202200402000527Z40862-W09LGSok to use 202200402000544Z40803-W05LGSok to use 202200402000566Z40803-W05HighIddReplaced 202200402000579Z40862-W09LGSok to use 202200402000587Z40803-W05TrimDACto rework 202200402000590Z40803-W03LowGReplaced 202200402000640Z40862-W02Redundancyto rework 202200402000681Z40862-W02LGSok to use 202200402000730Z40803-W01StrDelayReplaced 202200402000986Z41032-W13BlockLGHOLD 202200402000987Z41032-W13BlockLGHOLD 202200402000990Z41032-W13BlockLGHOLD 202200402001001Z41032-W13LGSok to use 202200402001007Z41032-W13BlockLGHOLD 202200402001009Z41032-W13BlockLGHOLD 202200402001078Z41032-w12BlockLGHOLD 202200402001178Z41032-w08BlockLGHOLD 202200402001190Z41032-w08Noisy??done?? 2022004020012210Z41032-w09LGSok to use 202200402001283Z40615-w19DeadHOLD 202200402001285Z40615-w19TimewalkHOLD 2022004020001111Z40859-W11LGS Replaced 202200402000136Z40859-W02 Mechanical Replaced 202200402000201Z40859-W014Token Replaced 202200402000218Z40859-W09LGS Replaced 202200402000217Z40859-W09BlockLG HOLD 2022004020002210Z40859-W09LowG to rework 202200402000359Z40859-W01Mechanical Replaced 202200402000356Z40859-W01TimeWalk Replaced 2022004020003910Z40859-W04Mechanical Replaced 202200402000392Z40859-W04LGS ok to use 202200402000396Z40859-W04LGS ok to use 202200402000412Z40802-W09LGS ok to use 202200402000469Z40803-W02LGS ok to use 202200402000470Z40862-W11NegOff to rework 202200402000486Z40803-W02AbnCal ok to use 202200402000489Z40803-W02LGS ok to use 2022004020005010Z40862-W11TimeWalk to rework 202200402000527Z40862-W09LGS ok to use 202200402000544Z40803-W05LGS ok to use 202200402000566Z40803-W05HighIdd Replaced 202200402000579Z40862-W09LGS ok to use 202200402000587Z40803-W05TrimDAC to rework 202200402000590Z40803-W03LowG Replaced 202200402000640Z40862-W02 Redundancyto rework 202200402000681Z40862-W02LGS ok to use 202200402000730Z40803-W01StrDelay Replaced 202200402000986Z41032-W13BlockLG HOLD 202200402000987Z41032-W13BlockLG HOLD 202200402000990Z41032-W13BlockLG HOLD 202200402001001Z41032-W13LGS ok to use 202200402001007Z41032-W13BlockLG HOLD 202200402001009Z41032-W13BlockLG HOLD 202200402001078Z41032-w12BlockLG HOLD 202200402001178Z41032-w08BlockLG HOLD 202200402001190Z41032-w08Noisy ??done?? 2022004020012210Z41032-w09LGS ok to use 202200402001283Z40615-w19Dead HOLD 202200402001285Z40615-w19Timewalk HOLD 2022004020001111Z40859-W11LGS Replaced 202200402000136Z40859-W02 Mechanical Replaced 202200402000201Z40859-W014Token Replaced 202200402000218Z40859-W09LGS Replaced 202200402000217Z40859-W09BlockLG HOLD 2022004020002210Z40859-W09LowG to rework 202200402000359Z40859-W01Mechanical Replaced 202200402000356Z40859-W01TimeWalk Replaced 2022004020003910Z40859-W04Mechanical Replaced 202200402000392Z40859-W04LGS ok to use 202200402000396Z40859-W04LGS ok to use 202200402000412Z40802-W09LGS ok to use 202200402000469Z40803-W02LGS ok to use 202200402000470Z40862-W11NegOff to rework 202200402000486Z40803-W02AbnCal ok to use 202200402000489Z40803-W02LGS ok to use 2022004020005010Z40862-W11TimeWalk to rework 202200402000527Z40862-W09LGS ok to use 202200402000544Z40803-W05LGS ok to use 202200402000566Z40803-W05HighIdd Replaced 202200402000579Z40862-W09LGS ok to use 202200402000587Z40803-W05TrimDAC to rework 202200402000590Z40803-W03LowG Replaced 202200402000640Z40862-W02 Redundancyto rework 202200402000681Z40862-W02LGS ok to use 202200402000730Z40803-W01StrDelay Replaced 202200402000986Z41032-W13BlockLG HOLD 202200402000987Z41032-W13BlockLG HOLD 202200402000990Z41032-W13BlockLG HOLD 202200402001001Z41032-W13LGS ok to use 202200402001007Z41032-W13BlockLG HOLD 202200402001009Z41032-W13BlockLG HOLD 202200402001078Z41032-w12BlockLG HOLD 202200402001178Z41032-w08BlockLG HOLD 202200402001190Z41032-w08Noisy ??done?? 2022004020012210Z41032-w09LGS ok to use 202200402001283Z40615-w19Dead HOLD 202200402001285Z40615-w19Timewalk HOLD

3 SCT Week -CERN- September 23, 2003 3 US ASIC’s Defects

4 SCT Week -CERN- September 23, 2003 4 LGS A study of the Large Gain Spread (LGS) effect was conducted in numerous ASIC ’ s to better understand the causes, effects, and possible solutions ISh and Vcc Icc FE DAC ’ s Areas of the Study

5 SCT Week -CERN- September 23, 2003 5 Icc Study – Icc vs (Icc-mean) Correlation Scatter plot of Icc versus the deviation of Icc from the mean Icc for each wafer (or gelpak) each chip is coming from All but one of the 17 chips with LGS can be identified by cutting at 5.5 (deviation from the mean Icc). This method can be used for pre-selecting chips before they are mounted on hybrids

6 SCT Week -CERN- September 23, 2003 6 Hybrid 20220040200013 Chip 2-5 Digital Tests Failure starting at 33 o C Hybrid tests: FullBypassTest: fails at Vdd = 3.5V but works fine at higher Vdd Wafer TV tests: At 40 and 50 MHz all chips TV(eff) = 1 and all Vdd(eff) =1 except chip S02: at 50 MHz and Vdd=3.3V for TV2 to TV5 eff =0 The timing of the token passing is quite critical. At higher temperatures the CMOS is slower, so it could get closer to the edge. It might be related to the quality of the clock signal. It might work at a different system. Three Point Gain Response at 37 o C

7 SCT Week -CERN- September 23, 2003 7 Hybrid 20220040200013 Wafer/Hybrid Comparison

8 SCT Week -CERN- September 23, 2003 8 Hybrid 20220040200020 chip 1 TOKEN Failure

9 SCT Week -CERN- September 23, 2003 9 Hybrid 20220040200021 chip 8 Large Gain Spread Chip started to work well at Vcc=3.7V - Voltage drop at the hybrid 50 mV Under wafer test (test performed at UCSC) works at nominal Vcc

10 SCT Week -CERN- September 23, 2003 10 Hybrid 20220040200021 Wafer/Hybrid Comparison

11 SCT Week -CERN- September 23, 2003 11 Hybrid 20220040200022 Chip 10 High Offset Example of High Offset in one chip

12 SCT Week -CERN- September 23, 2003 12 Hybrid 20220040200022 Wafer/Hybrid Comparison

13 SCT Week -CERN- September 23, 2003 13 Hybrid 20220040200035 Chip 6 (M8) High Gain (3Pt)

14 SCT Week -CERN- September 23, 2003 14 Hybrid 20220040200035 Chip 6 (M8) High Gain (After trim)

15 SCT Week -CERN- September 23, 2003 15 Hybrid 20220040200035 Chip 6 (M8) High Gain (after trim)

16 SCT Week -CERN- September 23, 2003 16 Hybrid 20220040200035 Chip 6 (M8) Time Walk Failure

17 SCT Week -CERN- September 23, 2003 17 Hybrid 20220040200035 Wafer/Hybrid Comparison

18 SCT Week -CERN- September 23, 2003 18 Hybrid 20220040200039 Chip 1 Large Gain Spread

19 SCT Week -CERN- September 23, 2003 19 Hybrid 20220040200039 Wafer/Hybrid Comparison

20 SCT Week -CERN- September 23, 2003 20 Hybrid 20220040200046 Chip 9 Large Gain Spread

21 SCT Week -CERN- September 23, 2003 21 Hybrid 20220040200046 Wafer/Hybrid Comparison

22 SCT Week -CERN- September 23, 2003 22 Hybrid 20220040200047 Chip 6 Trim DAC Loading

23 SCT Week -CERN- September 23, 2003 23 Hybrid 20220040200047 Chip 6 Trim DAC Loading

24 SCT Week -CERN- September 23, 2003 24 Hybrid 20220040200054 Chip 6 Large Gain Spread

25 SCT Week -CERN- September 23, 2003 25 Hybrid 20220040200054 Wafer/Hybrid Comparison

26 SCT Week -CERN- September 23, 2003 26 Hybrid 20220040200058 Trim DAC Loading

27 SCT Week -CERN- September 23, 2003 27 Hybrid 20220040200068 Chip 6 Large Gain Spread - cold

28 SCT Week -CERN- September 23, 2003 28 Hybrid 20220040200068 Wafer/Hybrid Comparison

29 SCT Week -CERN- September 23, 2003 29 Hybrid 20220040200068 Chip 6 Large Gain Spread - cold

30 SCT Week -CERN- September 23, 2003 30 Hybrid 20220040200073 Chip 0 Strobe delay

31 SCT Week -CERN- September 23, 2003 31 Hybrid 20220040200073 Wafer/Hybrid Comparison

32 SCT Week -CERN- September 23, 2003 32 Hybrid 20220040200010 High Offset (low gain)

33 SCT Week -CERN- September 23, 2003 33 Hybrid 20220040200010 High Offset (low gain)

34 SCT Week -CERN- September 23, 2003 34 Hybrid 20220040200010 High Offset (low gain)

35 SCT Week -CERN- September 23, 2003 35 Hybrid 20220040200010 High Offset (low gain)

36 SCT Week -CERN- September 23, 2003 36 Wafer/Hybrid Comparison Hybrid 20220040200010

37 SCT Week -CERN- September 23, 2003 37 Chip Response – New Cuts New cuts in the TrimRange Scan algorithm Noisy channels are now identified by the cut 1.15*(chip mean noise) Code to automatically exclude suspect data due to "8fC effect" The fitted range is adjusted to exclude points (charge > 5.0fC) for which the output noise is > 1.5*the mean output noise taken over all charges Channels with anomalous gain are now identified as follows: hi_gain channels have gain greater than (1.25 * mean_chip_gain) lo_gain channels have gain less than (0.75 * mean_chip_gain). This is in agreement with the gain cuts used during chip testing.

38 SCT Week -CERN- September 23, 2003 38 Overall Issues Gain non-uniformity (but mostly in agreement with wafer data) Wafer/Hybrid Comparison to confirm chips are within spec Possible chip pre-selection/better matching from looking at Wafer data of chips available to use Large Gain spread for several chips on a given hybrid at 0 o C (Hybrid LTT) after trim The threshold DAC has a tendency to saturate. This effect kicks in at slightly lower thresholds as a hybrid is cooled down. The 8fC point is out of line (off to higher threshold) during low temperature tests. For some hybrids it can be seen also at room temperature. This can effect the fitting of the response curve, hence the false high gain. Not including the 8fC point in the RC fit helps. Only 1 chip lost at cold (20220040200068) LTT time LTT- Burn-in test results show no time dependence for defects Any additional defects occur immediately: - 1 defective chips (large gain spread at cold) - 1 slow chip (at warm) - very few noisy/dead channels (almost none)

39 SCT Week -CERN- September 23, 2003 39 Summary HYBRIDS Defective Chips 12 chips defective after electrical testing + 2 damaged (chipped) Gain(6) Token(1) TW (1) Strobe Delay (1) TrimDAC (2) High Offset (1) Wafer/Hybrid comparison - used regularly and especially when anomalies are present - effective tool for chip selection New features/cuts in the software helps with anomalous chip response LT-Tests show no time dependence for defects: time could well be reduced to a few hours MODULES 19 modules built as of Feb 27 + 2 just assembled 17 modules completed with testing + 2 in progress PA defect on first batch of 29 hybrids - 15 hybrids already used in modules (11 rebonded) - 9 modules with 8-14 final unbonded channels (50% channel regained) - 14 hybrid still to be used but fixing bonds during rebonding -> good yield - 4 new hybrids used in modules HV boards communication/protocol more stable after Peter’s upgrade of the software No additional defect found in modules through sequence of tests

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