Presentation is loading. Please wait.

Presentation is loading. Please wait.

9/15/09 - L15 Decoders, Multiplexers Copyright 2009 - Joanne DeGroat, ECE, OSU1 Decoders and Multiplexer Circuits.

Similar presentations


Presentation on theme: "9/15/09 - L15 Decoders, Multiplexers Copyright 2009 - Joanne DeGroat, ECE, OSU1 Decoders and Multiplexer Circuits."— Presentation transcript:

1 9/15/09 - L15 Decoders, Multiplexers Copyright 2009 - Joanne DeGroat, ECE, OSU1 Decoders and Multiplexer Circuits

2 9/15/09 - L15 Decoders, Multiplexers Copyright 2009 - Joanne DeGroat, ECE, OSU2 Class 16 – Decoders, Multiplexers  Decoder Circuits  Multiplexer Circuits  Material from section 3-7 and 3-10 of text

3 Uses for the circuits  Distribution – information received from a single line is transmitted to one of 2 n possible output lines. Called de-multiplexing.  Consider some other specific uses. 9/15/09 - L15 Decoders, Multiplexers Copyright 2009 - Joanne DeGroat, ECE, OSU3

4 Implement an adder  Or actually any truth table by just ORing the function’s 1 outputs together. 9/15/09 - L15 Decoders, Multiplexers Copyright 2009 - Joanne DeGroat, ECE, OSU4

5 The priority encoder.  A priority encoder outputs the binary value of the most significant input line active.  Also have a ‘valid’ V output to indicate that the data lines are valid. 9/15/09 - L15 Decoders, Multiplexers Copyright 2009 - Joanne DeGroat, ECE, OSU5

6  Table and digital circuit implementation Priority Encoder circuit 9/15/09 - L15 Decoders, Multiplexers Copyright 2009 - Joanne DeGroat, ECE, OSU6

7 Mux and logic functions  A m input multiplexer can implement any of the logic functions n-bits where 2 n ≤ m.  Example for n=3 is the 1-bit binary adder implemented by using two 8-to-1 multiplexers. 9/15/09 - L15 Decoders, Multiplexers Copyright 2009 - Joanne DeGroat, ECE, OSU7

8 The adder.  Truth table and mux connection. (Fig 3-29 demystified) 9/15/09 - L15 Decoders, Multiplexers Copyright 2009 - Joanne DeGroat, ECE, OSU8

9 Mux implementation in general  Have the truth table for n variables  Have a multiplexer with n select inputs  Simply map the 0’s and 1’s from the truth table to the appropriate inputs.  Don’t cares could be connected either to power or ground.  “From the previous, a 4-to-1 multiplexer can implement any of the logic functions of 2 inputs.” 9/15/09 - L15 Decoders, Multiplexers Copyright 2009 - Joanne DeGroat, ECE, OSU9

10 Class 16 assignment  Covered sections 3-7 through 3-10  Problems for hand in none  Problems for practice 3-28, 33, 37, 44, 46, 48 (same as Class 15)  Reading for next class: sections 4-1, 4-2 9/15/09 - L15 Decoders, Multiplexers Copyright 2009 - Joanne DeGroat, ECE, OSU10


Download ppt "9/15/09 - L15 Decoders, Multiplexers Copyright 2009 - Joanne DeGroat, ECE, OSU1 Decoders and Multiplexer Circuits."

Similar presentations


Ads by Google