1. Advanced Digital Design Limits of Synchonous Design by A. Steininger and M. Delvai Vienna University of Technology

2. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 2 Outline Defining the Ideal Design Style Defining the Ideal Design Style Timed Communication Model Timed Communication Model Control Flow Conditions Control Flow Conditions Classification of Sychronous Design Classification of Sychronous Design Benefits of Synchronous Design Benefits of Synchronous Design Problems with Synchronous Design Problems with Synchronous Design Evaluation Evaluation

3. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 3 Resume 2 In practice temporal relations DO matter for a design. In practice temporal relations DO matter for a design. Boolean logic is not capable of expressing them. Boolean logic is not capable of expressing them. This causes consistency problems, glitches and runts. This causes consistency problems, glitches and runts. We need other means of introducing the missing information. We need other means of introducing the missing information. This is exactly the purpose of a design style. This is exactly the purpose of a design style. recal l

4. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 4 „Root of all Evil“ gate receiving contradictory signals simultaneously on different inputs gate receiving contradictory signals simultaneously on different inputs runt pulse (marginal pulse in value or time domain) runt pulse (marginal pulse in value or time domain) potential metastability in storage loop potential metastability in storage loop propagation of runt and/or metastability propagation of runt and/or metastability „Byzantine“ interpretation of runt and/or metastability „Byzantine“ interpretation of runt and/or metastability

5. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 5 What we actually need SRCSNK f(x) When it is valid and consistent When SNK has consumed the previous one When can SNK use its input? When can SRC apply the next input?

6. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 6 Our Options We must only use consistent input vectors We must only use consistent input vectors How can we tell an input vector is consistent? How can we tell an input vector is consistent? (1) use TIME to mark consistent phases synchronous approach synchronous approach asynchronous/bounded delay asynchronous/bounded delay (2) use CODING to add information asynchronous/delay insensitive asynchronous/delay insensitive

7. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 7 A Fair Comparison The purpose of a design style is to provide information for flow control. The purpose of a design style is to provide information for flow control. Boolean Logic alone cannot provide this information. Boolean Logic alone cannot provide this information. Severe technological problems force us to question the current (synchronous) design practice. We shall focus on that. Severe technological problems force us to question the current (synchronous) design practice. We shall focus on that. Alternatives must be evaluated very critically with respect to improvements concerning power, area, robustness, ease of composition, testability and performance. Alternatives must be evaluated very critically with respect to improvements concerning power, area, robustness, ease of composition, testability and performance.

8. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 8 The market demands … … faster chips („performance“) … faster chips („performance“) … smaller chips („embedded“) … smaller chips („embedded“) … cheaper products („consumer prod.“) … cheaper products („consumer prod.“) … more functions („features“) … more functions („features“) … battery supply („mobile“) … battery supply („mobile“) … robust operation („reliable“) … robust operation („reliable“)

9. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 9 Technology‘s Answer Miniaturization makes chips … Miniaturization makes chips … … faster … faster … smaller … smaller … cheaper … cheaper … more complex & powerful … more complex & powerful  … (ultimately) more power-hungry  … more error-prone

10. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 10 Vizualizing Miniaturization n Transistors 1995 n Transistors 2000 n Transistors 2005 n Transistors 2010

11. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 11 The Chip Design Crisis designer productivity gap hard physical limits impede miniaturization excessive test complexity heat problems power delivery problems increasing transient fault rates hard physical limits impede speed-up increasing NRE costs short time-to-market Do we need a new („revolutionary“) design approach?

12. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 12 The MOS Transistor n-channel enhancement FET contacts gate oxide n+ substrate channel L W T OX

13. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 13 Scaling Theory „Scaling technology by  scales… area by 1/  2 area by 1/  2 transistor current by1/  transistor current by1/  transistor power by1/  2 transistor power by1/  2 power density (pwr/area) by 1 “ power density (pwr/area) by 1 “ This is no more true for tech- nology nodes below 100nm!

14. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 14 Static Power Consumption gate tunnel currents ( currents over gate oxide) gate tunnel currents ( currents over gate oxide)  grow exponentially for thinner oxide subthreshold currents ( currents over „open“ transistor) subthreshold currents ( currents over „open“ transistor)  grow for lower threshold voltage leakage currents ( currents over reverse biased junction) leakage currents ( currents over reverse biased junction) can be decreased by SOI, e.g. can be decreased by SOI, e.g.

15. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 15 Dynamic Power Consumption switching currents (loading parasitic capacitances) switching currents (loading parasitic capacitances) crowbar currents (imperfect stack switching) crowbar currents (imperfect stack switching)

16. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 16 Power Consumption Trends processor power [W] 1000 100 10 1 0.1 0.01 196019701980199020002010 dynamic static [Furuyama, DSD’06]

17. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 17 Limits of Miniaturization charge of an electron does not scale e = -1,602. 10 -19 C charge of an electron does not scale e = -1,602. 10 -19 C size of an atom does not scale Si-Atom = 0.05nm size of an atom does not scale Si-Atom = 0.05nm wave length for lithography does not scale UV >150nm wave length for lithography does not scale UV >150nm statistics of band model does not scale: invalid for small populations (doping) statistics of band model does not scale: invalid for small populations (doping) exponential growth of tunnel currents exponential growth of tunnel currents linear growth of electrical field strength linear growth of electrical field strength …

18. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 18 Fundam. Speed Limitations EM wave propagation EM wave propagation Information can never travel faster than with speed of light. Charging effects Charging effects Charging of a capacitance with limited current takes time. Charge movement Charge movement Movement/diffusion of charges in a semiconductor occurs at limited speed.

19. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 19 Power Delivery Problems  need to deliver currents of many amps into chip extreme current density in bondings & power rails extreme current density in bondings & power rails  need to supply huge current spikes within ps parasitic inductances critical parasitic inductances critical buffer capacitances required buffer capacitances required noise margins reduced noise margins reduced

20. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 20 Time-to-market needs to be ever shorter needs to be ever shorter rapidly changing standards rapidly changing standards „last minute“ availability of crucial components/specs „last minute“ availability of crucial components/specs exploit market opportunities exploit market opportunities being late causes tremendous loss of profit being late causes tremendous loss of profit

21. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 21 Productivity Gap We cannot design as complex chips as we could manufacture need much better tool support need much better tool support need to combine pre-designed modules need to combine pre-designed modules log trans/chip trans/staff/time +59%/a (Moore) +21%/a [ITRS] t

22. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 22 Verification Need to make sure that implemen- tation matches specification: Need to make sure that implemen- tation matches specification: all desired functions available all desired functions available no undesired behavior no undesired behavior 70% of time spent on verification 70% of time spent on verification Model-based approach: Model-based approach: spec transformed into (high-level) model spec transformed into (high-level) model model properties formally verified model properties formally verified model is implemented in HW & SW model is implemented in HW & SW BUT: how check implementation vs. model??

23. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 23 Test Test complexity rises with more than O(n 2 ) with circuit complecity Test complexity rises with more than O(n 2 ) with circuit complecity It will soon cost more to test a transistor than to manufacture it It will soon cost more to test a transistor than to manufacture it log € cost/trans test costs -29%/a  const [ITRS] t

24. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 24 Transient Faults …occur 10…100 times more often than permanent faults today …occur 10…100 times more often than permanent faults today …originate from storage elements being upset (directly or indirectly) …originate from storage elements being upset (directly or indirectly) …can only be caused by disturbances with an energy larger than that stored in the affected cell …can only be caused by disturbances with an energy larger than that stored in the affected cell … are often caused by particle hits (single event upsets: SEUs) … are often caused by particle hits (single event upsets: SEUs)

25. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 25 Fault Rate Predictions energy stored in a storage element scales with energy stored in a storage element scales with feature size feature size power supply power supply energy distribution of particles is non-linear energy distribution of particles is non-linear significantly more particles towards lower energy significantly more particles towards lower energy fault potential largely increases with every technology node

26. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 26 Fault Mitigation stopping miniaturization stopping miniaturization is not an option is not an option technology (materials, shielding,…) technology (materials, shielding,…) keeps fault rate per transistor  constant keeps fault rate per transistor  constant = still overall increase per chip = still overall increase per chip robust circuit design robust circuit design requires different design techniques requires different design techniques system-level fault tolerance system-level fault tolerance current solution current solution expensive expensive

27. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 27 Ideal Design Method An ideal design method … minimizes power consumption minimizes power consumption miminizes circuit overhead miminizes circuit overhead naturally supports composability naturally supports composability naturally aids testability naturally aids testability yields robust circuits yields robust circuits yields fast circuits. yields fast circuits.

28. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 28 Solutions ahead? Many people envision a paradigm shift as the only solution Many people envision a paradigm shift as the only solution As the pain grows… As the pain grows… so does the willingness to perform such a shift so does the willingness to perform such a shift so does the incentive to come up with a novel solution so does the incentive to come up with a novel solution

29. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 29 What we actually need SRCSNK f(x) When it is valid and consistent When SNK has consumed the previous one When can SNK use its input? When can SRC apply the next input? recal l

30. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 30 Terminology consistent DW: all bits belong to the same context valid signal: result of function applied to consistent DW

31. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 31 Timed Comm. Model for details see: M. Delvai, A. Steininger. Solving the fundamental Problem of Digital Design – A Systematic Review of Design Methods, 9th Euromicro Conference on System Design, Dubrovnik 2006.

32. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 32 Timed Comm. Model

33. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 33 The Issue Condition Control TRGSRC: Have SRC issue the next data word such that the current one can still be safely consumed by SNK. Formal Condition: t invalid,x > t safe,x  src > -  invalid

34. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 34 The Capture Condition Control TRGSNK: Have SNK capture data only after it has become consistent. Formal Condition: t cons,x > t snkrdy,x  snk > -  snktrg

35. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 35 Our Options We must only use consistent input vectors We must only use consistent input vectors How can we tell an input vector is consistent? How can we tell an input vector is consistent? (1) use TIME to mark consistent phases synchronous approach / global time base synchronous approach / global time base asynchronous/bounded delay asynchronous/bounded delay (2) use CODING to add information asynchronous/delay insensitive asynchronous/delay insensitive

36. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 36 „If the problem originates from the time domain, why don‘t we solve it in the time domain!“ „If the problem originates from the time domain, why don‘t we solve it in the time domain!“ Process inputs only after they have become stable. Process inputs only after they have become stable. Use clock to signal these instants. Use clock to signal these instants. Synchronous Philosophy

37. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 37 Control by Global Time

38. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 38 clock periodactive clock edge recovery from transients * clock to output delay * combinational delay * routing delay, … setup/hold window HILO Synchronous Timing

39. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 39 The Synchronous Concept f(x) FF1FF2 T Clk „After some TIME T clk FF2 can use f(x)‘s output and at the same time FF1 can apply a new input“

40. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 40 The Implications Clock Period T Clk = Period  Clock Period T Clk = Period  Must be determined by static timing analysis Must be determined by static timing analysis Phase  =  (!) Phase  =  (!) this implies that this implies that  src = -( snktrg +  cons ) still we must guarantee still we must guarantee  src > - invalid (issue condition) therefore therefore  invalid >  snktrg +  cons This is not formally safe – but it works!

41. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 41 Benefits of Sync. Logic Simplicity improves productivity Simplicity improves productivity design on high level of abstraction design on high level of abstraction truth table with „previous state“ truth table with „previous state“ transients are irrelevent, all considered states are clearly defined transients are irrelevent, all considered states are clearly defined timing analysis separate, after design timing analysis separate, after design clear distinction between data and clock simplifies timing analysis clear distinction between data and clock simplifies timing analysis

42. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 42 Benefits of Sync. Logic (2) High implementation efficiency: High implementation efficiency: one single control signal for the complete system! one single control signal for the complete system! periodic clock is easy to generate periodic clock is easy to generate single-rail data coding single-rail data coding minimum number of transitions on the data rails minimum number of transitions on the data rails clock also provides a time base clock also provides a time base

43. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 43 Resume 1 Synchronous design does work Synchronous design does work billions of working designs billions of working designs Synchronous design is VERY efficient Synchronous design is VERY efficient wrt. design wrt. design wrt. implementation wrt. implementation So everything is solved So everything is solved Is it? Is it?

44. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 44 The Original Problem SRCSNK f(x) When it is valid and consistent When SNK has consumed the previous one When can SNK use its input? When can SRC apply the next input? recal l

45. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 45 What have we done? We have expressed a simple information related condition by means of complicated timing related parameters that we don‘t even know! DOES IT MATTER ? recal l

46. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 46 That damned traffic light YES! It does matter

47. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 47 That damned … Traffic light Traffic light number of waiting cars number of waiting cars Microwave oven Microwave oven temperature of the food temperature of the food Wiper Wiper visibility through the front shield visibility through the front shield Stairway light Stairway light presence of a person in the stairway presence of a person in the stairway

48. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 48 What‘s wrong? Often events define important points in time. Often events define important points in time. This does, however, not mean that the occurrence of the event can be a priori related to (absolute or relative) time. This does, however, not mean that the occurrence of the event can be a priori related to (absolute or relative) time. BUT: Time is relatively easy to measure BUT: Time is relatively easy to measure Therefore it is often much more efficient to establish such an indirect relation than to observe the actual event (that is sometimes invisible) Therefore it is often much more efficient to establish such an indirect relation than to observe the actual event (that is sometimes invisible) This starts to become annoying when the artificial relation between actual event and time model is too weak. This starts to become annoying when the artificial relation between actual event and time model is too weak.

49. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 49 The Synchronous Approach f(x) FF1FF2 T Clk „After some TIME T clk FF2 can use f(x)‘s output and at the same time FF1 can apply a new input“ Relating flow control to time in this way is convenient and effective, but in fact the implied relation does not (naturally) exist! We need to establish this relation artificially during design (timing optimization & constraints)

50. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 50 The annoying consequences need to determine clock period need to determine clock period circuit functionality is technology dependent circuit functionality is technology dependent considerable design efforts, large design loops considerable design efforts, large design loops need to make worst-case assumptions need to make worst-case assumptions necessarily pessimistic necessarily pessimistic no robustness wrt. exceeding them no robustness wrt. exceeding them need to maintain global synchrony need to maintain global synchrony clock distribution problems clock distribution problems power consumption problems power consumption problems

51. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 51 Can we predict Delay? after synthesis: logic depth after synthesis: logic depth complexity of operation complexity of operation optimization & mapping optimization & mapping after routing: interconnect after routing: interconnect geometrie (lengths, capacitances) geometrie (lengths, capacitances) vias, switches vias, switches during operation: actual values during operation: actual values process variations process variations temperature temperature supply voltage supply voltage recal l

52. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 52 Timing Analysis not possible before the end of the design flow (large iteration loops!) not possible before the end of the design flow (large iteration loops!) Design-Entry Synth. & Technol.-Mapping Partitioning & Placement Routing Manufact. Specification Validation Behavioral Simulation Postlayout-GL-Simulation Prelayout-GL-Simulation Test

53. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 53 Timing Analysis not possible before the end of the design flow (large iteration loops!) not possible before the end of the design flow (large iteration loops!) tight & safe esti- mation has become a major issue tight & safe esti- mation has become a major issue sync model reality transientssetup/hold

54. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 54 Timing Analysis not possible before the end of the design flow (large iteration loops!) not possible before the end of the design flow (large iteration loops!) tight & safe esti- mation has become a major issue tight & safe esti- mation has become a major issue feasible with „ideal“ clock net only feasible with „ideal“ clock net only original idea: avoid having to deal with transients current practice: timing analysis most difficult t PD,CLK CLK D D D D … t dly,DATA,1m t dly,DATA,2m t dly,DATA,km FF1 FF2 FFk FFm combin. logic

55. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 55 normally too pessimistic normally too pessimistic real, chip could run faster no tolerance when exceeded no tolerance when exceeded graceful degradation desirable    lim Worst-Case Assumptions

56. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 56 ! Performance Efficiency real computation time 2010050103020 lib: worst vs. typcrosstalk, IR dropprocess variation clock skew unbalanced stages [Cortadella, ICCD’04]

57. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 57 Clock Distribution clock distribution network widely spread over chip clock distribution network widely spread over chip minimization of delay & skew very tedious and costly minimization of delay & skew very tedious and costly A

58. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 58 ! Area Efficiency area proportion devoted to intended logic function area proportion devoted to necessary flow control overhead: clock network 45% [Wilton IEEE Jnl. SSC 2/2005]

59. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 59 Power Dissipation clock network con- sumes much energy clock network con- sumes much energy concurrent switching => current peaks => voltage drops concurrent switching => current peaks => voltage drops permanent switching => artificial activity permanent switching => artificial activity according to publications 40% (DEC, e.g.)

60. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 60 ! Power Efficiency dissipated power (total) static part dynamic part control part (dynamic only * ) power for intended function circuit utilization * [Duarte]

61. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 61 f E(f) max / CE A long clock rails are good antennas long clock rails are good antennas virtually all radiated energy is con- centrated to one single spectral line virtually all radiated energy is con- centrated to one single spectral line Electromagn. Interference

62. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 62 ! Composability each and every small change in the design requires a completely new timing analysis each and every small change in the design requires a completely new timing analysis a switch to a new technology completely changes the timing a switch to a new technology completely changes the timing interoperation between IP cores on a chip requires detailed specification (and matching) of both interoperation between IP cores on a chip requires detailed specification (and matching) of both logic function and logic function and timing behavior timing behavior

63. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 63 ! Robustness  metastability Issues  clock = single point of failure  non-redundant signal coding  no graceful degradation timing margins help masking faults timing margins help masking faults  but they are shrinking!  synchrony is a very strong assumption => it takes a lot of efforts to maintain it => „assumption coverage“ is lower

64. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 64 Experimental Results Fault Injection Results for SPEAR [Thesis Rahbaran]

65. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 65 Fault Masking Effects electrical masking electrical masking too short fault pulse is filtered out by (parasitic) low-passes too short fault pulse is filtered out by (parasitic) low-passes logical masking logical masking faults on masked gate inputs are irrelevant faults on masked gate inputs are irrelevant temporal masking temporal masking depending on design style signal values are considered only during defined windows; faults may go unrecognized when outside these windows depending on design style signal values are considered only during defined windows; faults may go unrecognized when outside these windows 0 0

66. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 66 Scan test turns sequential problem into combinational one => hard to beat! ! Testability

67. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 67 Conclusion An analysis of the data transfer process allows mapping the trigger conditions for data source and sink to the time domain, yielding an „issue condition“ and a „capture condition“. An analysis of the data transfer process allows mapping the trigger conditions for data source and sink to the time domain, yielding an „issue condition“ and a „capture condition“. This convenient solution is used by some design styles, in particular the synchronous design. This convenient solution is used by some design styles, in particular the synchronous design. This mapping is, however, not natural. This mapping is, however, not natural. As an alternative signal coding may be used to control the triggers of source and sink. As an alternative signal coding may be used to control the triggers of source and sink.

68. Lecture "Advanced Digital Design"© A. Steininger & M. Delvai / TU Vienna 68 Conclusion Synchronous design is extremely efficient wrt. design and testing. Synchronous design is extremely efficient wrt. design and testing. It establishes a relation between handshake events and time that becomes increasingly cumbersome. It establishes a relation between handshake events and time that becomes increasingly cumbersome. Weak points are inherent robustness and composability Weak points are inherent robustness and composability Power efficiency, area efficiency and performance efficiency are very good in principle, but limitations in clock distributions tend to foil these benefits. Power efficiency, area efficiency and performance efficiency are very good in principle, but limitations in clock distributions tend to foil these benefits.