1.  Seattle Pacific University EE 1210 - Logic System Design Standard Gates-1 Logic Chips HD74LS04P 1 2 3 4 5 6 78 9 10 11 12 13 14 HD74LS04P Actual circuit is on a small chip of silicon Package – Made of plastic or ceramic Pins are connected to chip with internal wires Pin number one is identified with a dot or notch Pins are numbered in a counter-clockwise fashion Standard chips use either TTL (Transistor-Transitor Logic), or CMOS transistors

2.  Seattle Pacific University EE 1210 - Logic System Design Standard Gates-2 Logic Chips – 7400 NAND 74LS00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Part number – 74xx00 is a 7400 Quad Nand Gate GND Vcc All chips have connections to Vcc (+5) and GND – Usually pins 14 and 7 There are four 2-input NAND gates in a 7400 LS – Low-Power Schottky TTL HC – CMOS HCT – TTL-compatible CMOS F – Fast TTL

3.  Seattle Pacific University EE 1210 - Logic System Design Standard Gates-3 Logic Chips – Inverters and NORs 1 2 3 4 5 6 7 8 9 10 11 12 13 14 GND Vcc 74LS04 1 2 3 4 5 6 7 8 9 10 11 12 13 14 GND Vcc 74LS02 74xx04 Hex Inverter74xx02 Quad NOR Gate

4.  Seattle Pacific University EE 1210 - Logic System Design Standard Gates-4 Logic Families 5V TTL Standard Low-Power Schottky – LS Fast - F 5V CMOS Standard - HC HCT – TTL compatible 0 5 4 3 2 1 Input Voltage 0 5 4 3 2 1 Output Voltage 0 5 4 3 2 1 Input Voltage 0 5 4 3 2 1 Output Voltage High Low High Low High Low High Low WARNING – Don’t mix TTL and HC

5.  Seattle Pacific University EE 1210 - Logic System Design Standard Gates-5 Finding Info on Chips Search online Enter the part number, with family code “74LS02 datasheet” “74HC00 datasheet” Basic functionality is easy to find Timing info may require looking up the exact manufacturer

6.  Seattle Pacific University EE 1210 - Logic System Design Standard Gates-6 Making a logic circuit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 GND Vcc 74LS04 74LS00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 GND Vcc A C A B F T1T1 T2T2 T1T1 T2T2 A C A B F GND +5 ABC F T1T1 T2T2 Convert to NANDs

7.  Seattle Pacific University EE 1210 - Logic System Design Standard Gates-7 Prototyping Breadboards a b c d e f g h i j + - + - + - + - +/- Are connected in columns. Used for connections to +5V and GND. Note: On some boards, they are split in the middle a/b/c/d/e and f/g/h/i/j are connected in rows. Used for connecting to chips. Note: They are not connected in the middle. Connections for Power/GNDConnections from chip to chip 74LS0474LS0274LS00 To +6V