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In-System Programmable PROGRAMMABLE ANALOG CIRCUITS ispPAC™
PowerPAC1208
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Agenda What is PowerPAC Details of PowerPAC Application Example
PAC-Designer – Demonstration Summary
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What is PowerPAC? ispPAC-POWR T44I Single Chip, In-System Programmable Power Sequencing & Monitoring Solution
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Where Does PowerPAC Fit On a Board?
Board Power 3.3V Supply 3.3V Section Multi-Supply 2.5V Circuit Board Sequenced 3.3 V Bus 3.3 V Input 1.8V 1.8V Bus LDO/ Supply Brick Supply Sequenced 2.5 V Bus Brick 2.5V FET/ LDO/Brick Enable Monitor Supervisory PowerPAC Voltages Signals
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PowerPAC1208 Block Diagram
Vdd = 2.25V to 5.5V Comparator Monitors Supply Outputs for Voltages External Sequence Controller CPLD 32 I/P & 16 Macrocell GLB Comparator Outputs High Voltage PowerPAC Logic Expansion VMON1 8 COMP1 & Control VMON2 COMP2 VMON3 COMP3 VMON4 COMP4 VMON5 Analog COMP5 VMON6 Inputs COMP6 VMON7 12 COMP7 VMON8 4 COMP8 VMON9 VMON10 VDD VMON11 HVOUT1 VMON12 HVOUT2 5 HVOUT3 FET Gate HVOUT4 250kHz 4 Drive / Internal IN1 Supervisory IN2 Digital OSC OUT5 Signal Logic IN3 Inputs OUT6 4 Timers Outputs OUT7 IN4 OUT8 Monitors Digital Supervisory Signals External Clock for Signals CLKIO JTAG Longer Time Delay 44-Pin TQFP
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PowerPAC’s Ruggedized Operation
Reliable Operation During Rough Power Supply Conditions Fast Rise Slow Ramp Non-Monotonic Ramp Sudden Dips in Supply Voltages Supply Voltage Range of Operation– 2.25V to 5.5V All DC and AC Parameters are Specified Down to 2.25V All Outputs Operate down to 1.9V Supply Input Glitch Immunity up to 20 s Industrial Temperature Range
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Features of PowerPAC1208 Analog Section:
12 Comparators – To Monitor Power Supply Voltages Individual Programmable Threshold 1% Threshold Resolution around 6 popular Power Supply Voltages 192 Steps Input Hysteresis Auto-Scales With Monitor Voltage Maintains Noise Tolerance Across Supply Voltages Programmable Input Glitch Filter 4 FET Drivers – To Enable/Sequence Power Supply Bus Power Supply Ramp Rate - Controlled To Meet Device Specifications Programmable Output Current Feed – 500 nA to 50 uA – 32 steps Internally Charge Pumped – To Reduce MOSFET On-Resistance Configurable High Voltage for FET Driver – 8V to 12.5V – 8 Steps To Meet Gate Voltages for Different Power Supplies Configurable as Open Drain Output - For Digital Control
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PowerPAC1208 Programmable Delays
3.3V Supply 2.5V Supply 2ms 4ms 8ms 16ms Delay Composite Plot Showing 6 Different Delay Settings for the 2.5V Control Signal.
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PowerPAC1208 Slew Rate Control
Select Output Mode 3.3V Supply 2.5V Supply FET Driver Ramp Current and Max Voltage Composite Plot Using Different Ramp Currents for the 2.5V HVOUT Signal.
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Features of PowerPAC1208 – Cont’d
Digital Section: 16 Macrocell CPLD (Similar to ispMACH4000 Macrocell) Supports Supply Sequencing & Supervisory Signal Generation Ruggedized to Operate Reliably Under Noisy Environments 32 Input, 80 Product Term 250 kHz Oscillator – Flexible Timing Generation Pre-scalar for Slower PLD Operation Down to 2 kHz Clock 4 Programmable Timers Programmable Duration –Implements Delays for Power Supply Stabilization, Watchdog Timers, etc. 32 us to 512 ms with Internal Oscillator – 16 Steps Extend Timer Duration to Any Length Using External Clock Controlled by Macrocell Output – Reuse the Same Timer Under Different Logic Conditions
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Features of PowerPAC1208 – Cont’d
4 Digital Inputs Logic Input Standards Compliance Set By VDDINP Pin CMOS 5.0, LVCMOS 3.3, LVCMOS 2.5 4 Open Drain Outputs Supports Various Interface Standards Through External Pull-Ups 8 Comparator Direct Outputs Logic Expansion Drive Voltage Tracking Transistors Easy interface to Existing System Level Initialization Logic
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Complete & Flexible Power Sequencing & Monitoring Solution
Summary Complete & Flexible Power Sequencing & Monitoring Solution Integration Combines Analog & Digital Functionality Ruggedized Operation Increases Reliability Programmability Threshold Voltages CPLD for Sequencing, Monitoring Logic Implementation FET Driver for Controlling Power Supply Ramp Rate Programmable Long-Duration Timers
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Application Example
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Example Power Supply Problem Statement
Power Sequencing Application Supervisory Signal Generation Activate Power_OK signal and Deactivate CPU-Reset Signal After all Supplies are Turned On Monitoring Power Supply Voltages If Any Voltage Drops Below Threshold, Reset Processor & Remove All Power
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Supervisory Signal Generation
Example Application Device 3.3V Power Bus 3.3V 1.8V CPU Core Voltage Input LDO Supply 2.5V ASIC & I/O Voltage Bus Brick Other Board Circuitry LDO1V8_En Brick2V5_En FET_Driver_3V3 Vin_3V3_Over3V2 Dev_1V8_Over1V7 Dev_2V5_Over2V4 CPU_Reset PowerPAC1208 Power_Good Power Supply Monitoring , Sequencing , & Supervisory Signal Generation
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Power Supply Sequence Steps
CONDITION/ACTION COMMENTS 1 Wait for 3.3 V supply > 3V Wait for 3.3V to stabilize within 10% margin 2 Enable 1.8 LDO = 1, CPU-Reset = 0 Hold the reset active when the CPU is powered on 3 Wait for 1.8V > 1.7V Wait for LDO voltage to stabilize 4 Enable 2.5V Power Supply Brick = 1 5 Wait for 2.5V supply > 2.375V Wait for the 2.5V to stabilize within the 5% margin 6 Power-Good signal = 1 Signal to FPGA to Load 7 Wait for 50 ms Wait for FPGA to load, and the ASIC to initialize 8 CPU-Reset = 1 CPU is now ready to execute 9 <Board Power up complete> 10 POWER-DOWN SEQUENCE Enter here under fault condition 11 CPU-Reset = 0 Prevent CPU from corrupting memory 12 Enable 2.5V Power Supply Brick = 0; Enable 1.8 LDO = 0 Remove the 2.5V power supply and remove the 1.8V supply to CPU 13 Jump to step 13 Stop
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Handling Power Supply Fault Condition
Monitor Condition Outputs Go to Sequence Step Comments IF (Power_good = 1) AND (( 3.3V is < 3V) OR (2.5V < 2.375) OR (1.8V < 1.71)) Power_good signal = 0 Step 10 If one of the power supply voltages drops below lower limit, initiate shut down
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PAC-Designer 1.9.1 Demonstration
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What’s New in PAC-Designer 1.9.1 - For PowerPAC
Hierarchical Design Entry Easy System Interface Parametric Specification PAC LogiBuilder - The Logic Wizard Map Power Supply Sequencing & Monitoring Steps Directly into Design Advanced Features: Supply Glitch Monitor, Watchdog Timer, etc. Fits Code Into PLD Automatically Lattice Simulator Waveform Viewer Waveform Stimulus Editor
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First .. High Level Design Entry
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Configure Supply Voltage Monitoring Threshold
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Summary – Hierarchical Design Entry
Easy System Interface Parametric Specification Setting Monitor Threshold Voltage, Signal Names FET Gate Drive Voltage & Current Selecting Internal/External Clock & Timer Values
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Second: Build Sequence Control Program
No New Language to Learn! Double-Click On the Line & Pick Instructions From Menu
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And .. Build Expressions Interactively
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Easily Translates Into PAC LogiBuilder Program
Detailed Application Requirement Easily Translates Into PAC LogiBuilder Program
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And.. Fits into a PowerPAC1208!
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PAC LogiBuilder - Summary
Intuitive Translation of Power Sequencing & Monitoring Requirement No New Language to Learn Simple Point & Click Instructions Power Supply Sequence Design Power Supply Monitor Design Supervisory Signal Specification 5 Basic Instructions & 3 Advanced Instructions Fitting the Design into On-board CPLD of PowerPAC
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Third: Create Stimulus Using Waveform Editor
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Verify the Design Using The Lattice Simulator
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Finally: “ispProgram” the Device
PowerPAC Evaluation Board JTAG ispDOWNLOAD Cable Same Cable Used For Programming Lattice CPLD
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PAC-Designer 1.9.1 - Summary
Hierarchical System Interface Definition Easy System Interface Parametric Specification PAC LogiBuilder Easy Design of Sequencing & Monitoring Intuitive Point & Click Instructions Lattice Waveform Editing & Simulation Verify Design Before Wiring up Prototype
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Additional Documentation…..
Application Notes Sparkle Sheet DataSheet PAC-Designer 1.9.1
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PowerPAC1208 & PACsystem ispPAC-POWR1208-01T44I
Available in 44-Pin TQFP Package Only Temperature Range - -40C to +85C Evaluation – PAC-SystemPOWR1208 Evaluation Board – PAC-POWR1208-EV PAC-Designer Software CD Includes Latest Datasheets & Applications Notes Price: $149
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Summary Integration Software Programmability
PowerPAC Offers Single-Chip Solution For Sequencing & Monitoring Board Space Savings Increased Reliability Software Simplifies Interfacing PowerPAC to Various Power Supplies & FETs PAC LogiBuilder – Easy Implementation of Sequencing and Monitoring Algorithms Wave Stimulus and Waveform View Ease Verification Programmability Flexibility in Sequencing, Threshold Voltage, Delays, FET Gate Driver Inventory Reduction – PowerPAC can be Tailored to Control Many Types of Power Supply Arrangements EECMOS Technology + ISP Allows Easy Tuning of Design
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