1. The Functions of Operating Systems Interrupts

2. Learning Objectives Explain how interrupts are used to obtain processor time. Explain how processing of interrupted jobs may later be resumed. Identify typical sources of interrupts Describe algorithms and data structures associated with interrupts.

3. The simplest way of obeying instructions Sometimes the normal order of operation is changed by an interrupt. See next slide.

4. Interrupts Signals sent to the processor by devices / programs indicating that they require the attention of the processor. Due to errors or because of speed mismatch implications. Due to errors or because of speed mismatch implications. i.e. In order to save time, perform other tasks and wait to be interrupted by the I/O device when it is ready to continue.

5. Types Of Interrupts

6. I/O or Hardware interrupt Generated by hardware (I/O devices) to signal a service request (allows resolution of speed mismatch implications) or an error has occurred. E.g. E.g. Printer has emptied the buffer and wants it refilled. Printer is out of paper or is not connected. Close down safely in the event of a power failure from: A Uninterruptible Power Supply (UPS) which took over when the main electricity was lost but now its rechargeable power supply is running low. A Uninterruptible Power Supply (UPS) which took over when the main electricity was lost but now its rechargeable power supply is running low. The device which measures how much power is still left in a laptop battery informs the processor it is running low. The device which measures how much power is still left in a laptop battery informs the processor it is running low.

7. Timer / Clock Interrupt Generated at fixed intervals. Allows for display refresh and to control access to processor in multi-access or multi- programming system.

8. Program interrupt Generated due to an error in a program: Violation of memory use (trying to use part of the memory reserved by the OS for another use). Violation of memory use (trying to use part of the memory reserved by the OS for another use). An attempt to execute an invalid instruction (e.g. division by zero). An attempt to execute an invalid instruction (e.g. division by zero).

9. Terms Job / Process / Task / Program are all equivalent terms. Cycle is an instruction in a job / process / task / program.

10. Managing interrupts After the execution of an instruction (current cycle), the processor must see if an interrupt has occurred and service it. i.e. Obey a new set of instructions.

11. Type/Source of interrupt is checked and priority (different types have different priorities) of interrupt compared with current job. How this priority is decided is called scheduling and is dealt with in the next presentation. schedulingnext presentationschedulingnext presentation

12. If higher:

13. Masking / Disable equal or lower priority interrupts Mask out, refuse or disable all interrupts of an equal or lower priority than the current interrupt being serviced. Effectively meaning that any further interrupts will (in the execution of the current one) have to be of a higher priority if it is to interrupt the current interrupt. Effectively meaning that any further interrupts will (in the execution of the current one) have to be of a higher priority if it is to interrupt the current interrupt. This is done by using a Programmable Interrupt Controller (PIC) which is separate from the processor. All interrupts have to state their Interrupt Priority Level (IPL) and the PIC does not pass on any new interrupts to the processor unless they have a higher IPL (lower priority interrupts are therefore simply ignored). This allows the current interrupt to be executed without having to waste time considering equal or lower priority interrupts. http://en.wikipedia.org/wiki/Interrupt_handler How this priority is decided is called scheduling and is dealt with in the next presentation. schedulingnext presentationschedulingnext presentation

14. How can the interrupted program be resumed from where it left off when the interrupt has been serviced? The state of the current job is saved by saving the contents of all the registers (small, permanent storage locations within the CPU used for a particular purpose) in the processor so that the processor can use them to service the interrupt but can load their contents back in to resume the job being interrupted once the interrupt has been serviced. The first register to be saved is one called the Program Counter which holds the address of the next instruction. The first register to be saved is one called the Program Counter which holds the address of the next instruction. Then the other registers are saved. Then the other registers are saved. For more information see the. For more information see the Von Neumann Architecture Presentation, later in this course.Von Neumann Architecture Presentation

15. Scheduling processes and the Process Control Block (PCB). Each job is allocated a block of memory called a process control block. This will hold the following information: Process Identity Number. Current state of the job when the job was last left. The contents of each register when the job was last left on a stack. What priority the process has. Estimated time for the job to be finished. It's current status, whether it is waiting for I/O, whether it's waiting to use the CPU. Pointers pointing to areas in memory reserved for this process and resources that could be used. When a process is stopped, the above details are loaded into the Process Control Block, ready for next time the process uses CPU time. When that time comes, the contents of the PCB are moved into the CPU and the process repeats itself!

16. Interrupt Service Routine (ISR) Place the current job in a “queue of interrupts” (position depends on its type/source and priority). An appropriate interrupt service routine (ISR), depending on the type and actual task of the interrupt, is loaded and run. Device driver in case of devices. Device driver in case of devices. Exception / signal / trap handler in case of software interrupts. Exception / signal / trap handler in case of software interrupts. OK, I have been interrupted. Now the CPU asks the hardware: 'What do you want me to do'? In other words: 'Which interrupt service routine should I run?' Interrupt is serviced by the processor. How this priority is decided is called scheduling and is dealt with in the next presentation. schedulingnext presentationschedulingnext presentation

17. Enable ALL interrupts When the interrupt is complete the processor will start considering all interrupts of a lower priority. i.e. enable or restore or unmask all equal and lower priority interrupts. i.e. enable or restore or unmask all equal and lower priority interrupts. Restore the contents of the registers for the next process in the queue of interrupts. Resume this process.

18. If an ISR is being run (lower priority interrupts are being masked) then it is ignored until the current interrupt is finished then its priority is compared to jobs in the queue, if lower than the next waiting job then or otherwise: Allocate the job a position in a job queue according to its priorities. If equal or lower: How this priority is decided is called scheduling and is dealt with in the next presentation. schedulingnext presentationschedulingnext presentation

19. Summary: 1.Disable interrupts of a lower priority. 2.Save the contents of the program counter on a stack in the Process Control Block. 3.Save all other registers and any other information needed to resume the current process. 4.Load and run the appropriate Interrupt Service routine (ISR). 5.If a higher priority interrupt is received then go to step 1. 6.When ISR is complete enable all interrupts of a lower priority and complete the task next in the queue of interrupts. When the next task has been chosen: 7.Restore all other registers. 8.Restore the Program Counter. 9.Continue execution of the interrupted original process.

20. http://www.scriptoriumdesigns.com/embedded/interrupts.php Also note: Some websites like the one above state that only the PC is saved before running the ISR and that it is part of the ISR’s job to save any of the other registers it will use; so that the previous job can resume from where it left off. This is so other registers are not saved unnecessarily as only the PC will definitely be changed (the address of the next instruction). If this is so, steps 3 & 4 and 6 & 7 (as the ISR would have to restore the registers it saved) on the previous slide, should be swapped round. This appears to be why mark schemes differ slightly from other sources in regards to the exact sequence, and therefore I predict some flexibility here. www.le.ac.uk/eg/fss1/lect_int_transparencies.doc www.le.ac.uk/eg/fss1/lect_int_transparencies.doc ‎ For more research:

21. Plenary State and explain all the different types of interrupt that may occur.

22. Types of Interrupt I/O interrupt Generated by an I/O device to signal that a job is complete or an error has occurred. Generated by an I/O device to signal that a job is complete or an error has occurred.E.g. Printer is out of paper or is not connected. Printer is out of paper or is not connected. Timer interrupt Generated at fixed intervals. Generated at fixed intervals. Allows for display refresh and to control access to processor in multi-access or multi-programming system. Allows for display refresh and to control access to processor in multi-access or multi-programming system.

23. Plenary How is an interrupt handled by a processor which is working on another task?

24. Summary: 1.Disable interrupts of a lower priority. 2.Save the contents of the program counter and all other registers on a stack in the Process Control Block. 3.Save any other information needed to resume the current process. 4.Load and run the appropriate Interrupt Service routine (ISR). 5.If a higher priority interrupt is received then go to step 1. 6.When ISR is complete enable all interrupts of a lower priority and complete the task next in the queue of interrupts. If continuing a previous task: 7.Restore all other registers. 8.Restore the Program Counter. 9.Continue execution of the interrupted original process.