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Computer Architecture Interrupts and Polling. Interrupts Nearly all modern processors of any size allow interruption by external devices. An interrupt.

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Presentation on theme: "Computer Architecture Interrupts and Polling. Interrupts Nearly all modern processors of any size allow interruption by external devices. An interrupt."— Presentation transcript:

1 Computer Architecture Interrupts and Polling

2 Interrupts Nearly all modern processors of any size allow interruption by external devices. An interrupt is an externally initiated transfer of program control. This means the CPU has no control over the arrival of an interrupt.

3 Interrupts The normal reason for such an interrupt is that some device, e.g. keyboard, disk, VDU, printer wants attention from the CPU. The device does not want to wait until the CPU takes the initiative, so it asks the CPU to stop what it is doing and turn its attention to the interrupting devices.

4 Interrupts The CPU has to be designed to detect the presence of an interrupt signal at least between each instruction and perhaps within an instruction. A CPU that can be interrupted within an instruction, breaking the instruction midway, is called restartable.

5 Interrupts The interrupt signal is a physical event on an interrupt request line. The CPU usually has some way of disabling or masking an interrupt if it is about to do a piece of work that should not be interrupted.

6 Interrupts To ensure the CPU can resume the interrupted program once the interrupt has been serviced, it must store any registers that could be overwritten by the interrupt service routine, also known as the interrupt handler. At the very least the program counter must be preserved.

7 Interrupts Any registers not automatically saved but subsequently required by the interrupt handler/service routine must be saved by the handler/service routine.

8 Interrupts Hardware interrupts can be prioritised by daisy chaining the interrupt acknowledge signal. Devices are all linked to the computer interrupt request input to produce a common interrupt request signal.

9 Interrupts When the CPU is ready to handle the interrupt request it sends an interrupt acknowledge signal to the device with the highest priority. If this device needs serviced it uses the signal itself, but if it does not need serviced it passes the signal on to the second device, and so on down the line.

10 Interrupts More complex interrupt controllers allow different priority levels of interrupt. There may be three different levels of interrupt, and devices connected to interrupt lines at a higher level are allowed to interrupt the servicing of devices at a lower level. A device at the same level has to wait until the interrupt handler is free.

11 Interrupts There are four main methods of controlling and synchronising input / output outside its domain where devices cannot utilise the system clock: 1. Program control I/O or Polling 2. Interrupt driven I/O 3. Direct Memory Access 4. Channel I/O

12 Interrupts Factors that need to be considered when choosing a method are: 1. Speed of the device. 2. Demand of the program on the processor. 3. Hardware complexity. 4. Software complexity.

13 Program Controlled I/O More commonly known as POLLING. Each device has registers for data, for status and control information. The data register is used to transfer data such as ASCII code for a character to be printed, while the status register is used to convey information, e.g. printer busy or out of paper.

14 Program Controlled I/O It is possible for the CPU to find a device status by interrogating the device status register. For example, if a string of characters are to be printed, the first character is sent to the printer’s data register, the CPU goes into a wait loop, continually checking the printer’s status register until printer ready to receive next character.

15 Program Controlled I/O Clearly, this method is a waste of CPU time and is only suitable for systems where this is of no consequence. In most systems it is better for the CPU to send the first character and get on with something else until the device sends a signal to say it is ready to accept more data.

16 Interrupt Driven I/O The I/O device issues an interrupt request signal to the CPU. The CPU will normally stop what it was doing, storing information required to restart from the same place after processing is completed for device request. Control is then passed onto interrupt service routine which receives the information from the I/O device.

17 Interrupt Driven I/O The CPU sends an acknowledgement to the device. When the ISR has finished it will first restore any registers it required to use to complete its task before passing control back to the CPU.

18 Direct Memory Access DMA is the name given to a method by which blocks of data can be sent from memory to a device and vice versa without detailed attention by the CPU. CPU is not required to handle numerous interrupts. DMA requires another bus controller device called a DMA controller.

19 Direct Memory Access DMA controller is able to work autonomously after it has been initialised by the CPU. Typically the DMA controller has 4 registers, a memory start address, a count of the number of words to be transferred, a device identifier and a direction flag to indicate input or output.

20 Direct Memory Access The DMA controller can be left to get on with a job until it interrupts the CPU on completed transfer. Considerable gain is achieved in relieving the CPU of I/O processing. But transfer of data still requires the data bus and therefore slows down access of CPU to memory. This deprivation of CPU by another bus controller is called cycle stealing.

21 Direct Memory Access Some DMA controllers match their use of the address and data buses to fit in with periods in an instruction cycle when the buses are not in use.

22 Direct Memory Access If a processor without DMA can process 15000 information packets per second with 50 % of its time taken up with transfer of packets and storage of data. When adding a DMA controller transfer time is reduced to 10%. Therefore, the processor working at 100% will process 15000 + (15000 – (15000 * 0.10) = 28500 packet per second

23 DMA V’s Non-DMA

24 Channel I/O Channel I/O controllers or I/O processors have been a feature of larger machines for quite a while. They are really processors dedicated to running programs devoted to the I/O task. The use of these controllers reduces the involvement of the CPU even further.

25 I/O additional Resources http://ncca.bournemouth.ac.uk/CourseI nfo/BAVisAn/Year1/CompSys/IO/


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