1. Regularity-Constrained Floorplanning for Multi-Core Processors Xi Chen and Jiang Hu (Department of ECE Texas A&M University), Ning Xu (College of CST Wuhan University of Technology) ISPD 2011

2. Outline Introduction Regularity issue Problem formulation and contributions Preliminaries Regularity in sequence pair and algorithm Experimental results and conclusions

3. Introduction Multi-core to Many-core era  CPU and GPU Homogeneous to Heterogeneous era  IBM Cell processor, Intel i5, i7 Floorplanning of multi-core design in less cores can be handled manually. But, for now, it is more difficult.  Due to # cores, heterogeneous system, etc.

4. Introduction (cont.) If multiple identical cores are adopted, they are preferred to be placed in a regular array.  Design simplicity, modularity and easy management of physical resources

5. Regularity issue Like symmetrical layout in analog circuit, but still different. In analog placement, array blocks of the same type of device are compacted together in order to reduce the effect of spatially- dependent variations. In multi-core processor floorplanning, non- array blocks can be placed between array blocks and one group of array blocks can be placed inside of another group of array blocks.

6. Problem formulation Inputs  A set of n blocks, each with area A i where i = 1, 2, …n.  A set of i nets N 1, N 2,…, N i among the n blocks.  A set of k array groups G 1, G 2,…,G k. Each array group is a subset of the blocks that must be placed in a regular array. An array group is composed by blocks of identical size and shape, which are usually processor cores or memory cores.

7. Problem formulation (cont.) Goal and constraints  Construct a floorplan F that satisfies non- overlapping and the regularity constraint, and minimizes the cost.  The cores are required to be placed in an array, the shape of the array, which is decided by the number of rows and columns, is flexible.  The blocks in an array group do not have to be placed next to each other.

8. Contributions Algorithm is based on sequence-pair and simulated annealing.  On how to encode the regularity constraint in sequence-pair.  And how to achieve the regularity in packing procedure. Claims that this is the first work on regularity-constrained floorplanning.

9. Preliminaries Floorplan?  Floor + Plan An example  SUN Niagara-3 processor

10. GTX470↑ i7↓ Cell Processor↑ i5↓

11. Preliminaries (cont.) Floorplan representations  Slicing tree, B*-tree, Sequence pair, etc. Each of them represents the floorplan in relative order.

12. Preliminaries (cont.) Area computation  By the bonding rectangle

13. Preliminaries (cont.) Wirelength estimation  Clique model, star model, spanning tree, Steiner tree, half-perimeter (bonding box), etc.

15. Preliminaries (cont.) Sequence pair (SP) representation basics  Represent a packing by a pair of module permutations called sequence-pair (e.g., (s1,s2) = (abdecf, cbfade)).  Moves Swap two modules in the first sequence. Swap two modules in both sequences. Rotate a module.  x’ is after (before) x in both sequences ⇒ x’ is right (left) to x.  x’ is after (before) x in s1 and before (after) x in s2 ⇒ x’ is below (above) x.

16. Preliminaries (cont.) Packing in SP

17. Regularity in sequence pair In relative order  Some terms Common subsequence (CS) Reversely CS Regularity subsequence-pair (RSP) Row (column) based RSP

18. Example of CS and reversely CS A sequence-pair (, ) 3 CSs (0, 3), (1, 4) and (2, 5) for the 3 rows block 0, 1 and 2 form a reversely CS.

19. Lemma The necessary condition that m blocks lead to a p×q array floorplan  The m blocks constitute p common subsequences of length q and q reversely common subsequences of length p in the sequence-pair.

20. RSP and Row (column) based RSP RSP  A contiguous subsequence of length m that satisfies Lemma in a sequence-pair is called regularity subsequence-pair. Row (column) based RSP  A RSP where each (inversely) CS corresponding a row (column) is contiguous.

21. Embed non-array blocks

22. Rule 1 A non-array block can be inside both or neither of α and β sequences of a RSP. A non-array block cannot be inside one of α and β sequences but outside of the other for a RSP.

23. If violated rule 1…  (, ) is not allowed.

24. Rule 2 A non-array block can be inside both or neither of α and β part of a contiguous (reversely) common subsequence in a row (column) based RSP. A non-array block cannot be inside one of α and β part but outside of the other for a contiguous (reversely) common subsequence in a row (column) based RSP.

25. If violated rule 2… (, ) is not allowed.

26. Regularity in sequence pair (cont.) In packing  If no non-array block inside an array, i.e., no non-array block is inside a RSP, then the array can be pre-packed into a single object, with or without spacing.  If there is any non-array block inside an array, then the minimum uniform spacing is decided by the largest dimension among the non-array blocks.

27. Expansion

28. Algorithm In fact, typical sequence pair with SA is applied.  Move types and regularity encoding are the differences compared the typical one. Objective function where λ is a user-specified weight

29. Move types Changing the factorization of an array group.  For example, a 2×6 array can be changed to a 3×4 array or other factorizations. Changing the RSP for an array group between row- based and column-based. Moving a non-array block into (or outside) a RSP. Swapping two non-array blocks. Rotating a non-array block. Rotating all blocks in an array group. Swapping two blocks in the same array group.  Only affect wirelength

30. Flow Initial SP generation considering regularity. Apply SA for different results iteratively. Evaluate the cost after each move. Stop until the stopping criterions are reached.  Not mentioned in the text.

31. Experimental results Environment  C++ on Windows  2.5GHz Intel Core 2 Duo processor and 2GB memory Benchmarks  Modified MCNC and GSRC benchmarks Parameters  λ=0.5 and 0 for two different experiments

32. Experimental results (cont.) It is compared with manual prefix method since this is the first work.  Those blocks in the same array group are preplaced in the array manually and form a big block.  Apply conventional floorplanning with the big blocks and other blocks.

33. Comparison with λ=0.5 Since array blocks have many factorizations, results of MP are the most smallest from all factorizations.

34. Plotted results for comparison

35. Area minimization only (λ=0) The higher the area usage, the smaller the wasted space.

36. Visualized result n100 as an example  By the proposed approach  By the manual prefix

37. Conclusions Proposes a floorplan algorithm for regularity-constrained design. Regularity in SP representation Obtain better results compared with naïve method.