1. Lecture 6: Multiply, Shift, and Divide
Professor Mike Schulte
Computer Architecture
ECE 201

2. 1-bit ALU for MSB (correction)
The ALU for the MSB must also detect overflow and indicate the sign of the result. 7 2 1 3

3. MIPS instructions Instruction Example Meaning Comments
multiply mult $2,$3 Hi, Lo = $2 x $3 64-bit signed product
multiply unsigned multu$2,$3 Hi, Lo = $2 x $3 64-bit unsigned product
divide div $2,$3 Lo = $2 ÷ $3, Lo = quotient, Hi = remainder
Hi = $2 mod $3
divide unsigned divu $2,$3 Lo = $2 ÷ $3, Unsigned quotient & remainder
Move from Hi mfhi $1 $1 = Hi Used to get copy of Hi
Move from Lo mflo $1 $1 = Lo Used to get copy of Lo
shift left logical sll $1,$2,10 $1 = $2 << 10 Shift left by constant
shift right logical srl $1,$2,10 $1 = $2 >> 10 Shift right by constant
shift right arithm. sra $1,$2,10 $1 = $2 >> 10 Shift right (sign extend)
shift left logical sllv $1,$2,$3 $1 = $2 << $3 Shift left by variable
shift right logical srlv $1,$2, $3 $1 = $2 >> $3 Shift right by variable
shift right arithm. srav $1,$2, $3 $1 = $2 >> $3 Shift right arith. by variable

4. MULTIPLY (unsigned) Paper and pencil example (unsigned):
Multiplicand = 8 Multiplier = Product = 72
n bits x n bits = 2n bit product
Binary makes it easy:
0 => place ( 0 x multiplicand)
1 => place a copy ( 1 x multiplicand)
4 versions of multiply hardware & algorithm:
successive refinement

5. Unsigned Combinational Multiplier
Stage i accumulates A * 2 i if Bi == 1
Q: How much hardware for 32 bit multiplier?

6. How does it work? at each stage shift A left ( x 2)A0 A1 A2 A3 B0 A0 A1 A2 A3 B1 A0 A1 A2 A3 B2 A0 A1 A2 A3 B3 P7 P6 P5 P4 P3 P2 P1 P0
at each stage shift A left ( x 2)
use next bit of B to determine whether to add in shifted multiplicand
accumulate 2n bit partial product at each stage

7. Unisigned shift-add multiplier (version 1)
64-bit Multiplicand reg, 64-bit ALU, 64-bit Product reg, 32-bit multiplier reg
Shift Left
Multiplicand
64 bits
Multiplier
Shift Right
64-bit ALU
32 bits
Write
Product
Control
64 bits
Multiplier = datapath + control

8. Multiply Algorithm Version 1
Start
Multiplier0 = 1 1.
Test
Multiplier0
Multiplier0 = 0
1a. Add multiplicand to product &
place the result in Product register
M’ier: 0011 M’and: P:
1a. 1=>P=P+Mcand M’ier: 0011 Mcand: P:
2. Shl Mcand M’ier: 0011 Mcand: P:
3. Shr M’ier M’ier: 0001 Mcand: P:
1a. 1=>P=P+Mcand M’ier: 0001 Mcand: P:
2. Shl Mcand M’ier: 0001 Mcand: P:
3. Shr M’ier M’ier: 0000 Mcand: P:
1. 0=>nop M’ier: 0000 Mcand: P:
2. Shl Mcand M’ier: 0000 Mcand: P:
3. Shr M’ier M’ier: 0000 Mcand: P:
1. 0=>nop M’ier: 0000 Mcand: P:
2. Shl Mcand M’ier: 0000 Mcand: P:
3. Shr M’ier M’ier: 0000 Mcand: P:
Product Multiplier Multiplicand
2. Shift the Multiplicand register left 1 bit.
3. Shift the Multiplier register right 1 bit.
nth
repetition?
No: < n repetitions
Yes: n repetitions
Done

9. Observations on Multiply Version 1
1 clock per cycle =>  100 clocks per multiply
1/2 bits in multiplicand always 0 => 64-bit adder is wasted
0’s inserted in left of multiplicand as shifted => least significant bits of product never changed once formed
Instead of shifting multiplicand to left, shift product to right.

10. MULTIPLY HARDWARE Version 2
32-bit Multiplicand reg, 32 -bit ALU, 64-bit Product reg, 32-bit Multiplier reg
Multiplicand
32 bits
Multiplier
Shift Right
32-bit ALU
32 bits
Shift Right
Product
Control
64 bits
Write

11. Multiply Algorithm Version 2
3. Shift the Multiplier register right 1 bit.
Done
Yes: n repetitions
2. Shift the Product register right 1 bit.
No: < n repetitions 1.
Test
Multiplier0
Multiplier0 = 0
Multiplier0 = 1
1a. Add multiplicand to the left half of product &
place the result in the left half of Product register
nth
repetition?
Start
Multiply Algorithm Version 2
Product Multiplier Multiplicand 1: 2: 3: 1: 2: 3: 1: 2: 3: 1: 2: 3:
M’ier: 0011 Mcand: 0010 P:
1a. 1=>P=P+Mcand M’ier: 0011 Mcand: 0010 P:
2. Shr P M’ier: 0011 Mcand: 0010 P:
3. Shr M’ier M’ier: 0001 Mcand: 0010 P:
1a. 1=>P=P+Mcand M’ier: 0001 Mcand: 0010 P:
2. Shr P M’ier: 0001 Mcand: 0010 P:
3. Shr M’ier M’ier: 0000 Mcand: 0010 P:
1. 0=>nop M’ier: 0000 Mcand: 0010 P:
2. Shr P M’ier: 0000 Mcand: 0010 P:
3. Shr M’ier M’ier: 0000 Mcand: 0010 P:
1. 0=>nop M’ier: 0000 Mcand: 0010 P:
2. Shr P M’ier: 0000 Mcand: 0010 P:
3. Shr M’ier M’ier: 0000 Mcand: 0010 P:

12. Still more wasted space!
3. Shift the Multiplier register right 1 bit.
Done
Yes: n repetitions
2. Shift the Product register right 1 bit.
No: < n repetitions 1.
Test
Multiplier0
Multiplier0 = 0
Multiplier0 = 1
1a. Add multiplicand to the left half of product &
place the result in the left half of Product register
nth
repetition?
Start
Still more wasted space!
Product Multiplier Multiplicand 1: 2: 3: 1: 2: 3: 1: 2: 3: 1: 2: 3:
M’ier: 0011 Mcand: 0010 P:
1a. 1=>P=P+Mcand M’ier: 0011 Mcand: 0010 P:
2. Shr P M’ier: 0011 Mcand: 0010 P:
3. Shr M’ier M’ier: 0001 Mcand: 0010 P:
1a. 1=>P=P+Mcand M’ier: 0001 Mcand: 0010 P:
2. Shr P M’ier: 0001 Mcand: 0010 P:
3. Shr M’ier M’ier: 0000 Mcand: 0010 P:
1. 0=>nop M’ier: 0000 Mcand: 0010 P:
2. Shr P M’ier: 0000 Mcand: 0010 P:
3. Shr M’ier M’ier: 0000 Mcand: 0010 P:
1. 0=>nop M’ier: 0000 Mcand: 0010 P:
2. Shr P M’ier: 0000 Mcand: 0010 P:
3. Shr M’ier M’ier: 0000 Mcand: 0010 P:

13. Observations on Multiply Version 2
Product register wastes space that exactly matches size of multiplier
Both Multiplier register and Product register require right shift
Combine Multiplier register and Product register

14. MULTIPLY HARDWARE Version 3
32-bit Multiplicand reg, 32 -bit ALU, 64-bit Product reg, (0-bit Multiplier reg)
Multiplicand
32 bits
32-bit ALU
Shift Right
Product
(Multiplier)
Control
64 bits
Write

15. Multiply Algorithm Version 3
Start
Multiplicand Product
Product0 = 1 1.
Test
Product0
Product0 = 0
1a. Add multiplicand to the left half of product &
place the result in the left half of Product register
Mcand: 0010 P:
1a. 1=>P=P+Mcand Mcand: 0010 P:
2. Shr P Mcand: 0010 P:
1a. 1=>P=P+Mcand Mcand: 0010 P:
2. Shr P Mcand: 0010 P:
1. 0=>nop Mcand: 0010 P:
2. Shr P Mcand: 0010 P:
1. 0=>nop Mcand: 0010 P:
2. Shr P Mcand: 0010 P:
2. Shift the Product register right 1 bit.
32nd
repetition?
No: < 32 repetitions
Yes: 32 repetitions
Done

16. Observations on Multiply Version 3
2 steps per bit because Multiplier & Product combined
MIPS registers Hi and Lo are left and right half of Product
Gives us MIPS instruction MultU
What about signed multiplication?
easiest solution is to make both positive & remember whether to complement product when done (leave out the sign bit, run for 31 steps)
apply definition of 2’s complement
need to sign-extend partial products and subtract at the end
Booth’s Algorithm is elegant way to multiply signed numbers using same hardware as before and save cycles
can be modified to handle multiple bits at a time

17. Motivation for Booth’s Algorithm
Example 2 x 6 = 0010 x 0110: x shift (0 in multiplier) add (1 in multiplier) add (1 in multiplier) shift (0 in multiplier)
ALU with add or subtract gets same result in more than one way: 6 = – = –
For example
x shift (0 in multiplier) – sub (start string of 1’s) shift (mid string of 1’s) add (end string of 1’s)

18. 0 1 1 1 1 0 middle of run end of run beginning of run
Booth’s Algorithm
middle of run
end of run
beginning of run
Current Bit Bit to the Right Explanation Example Op
1 0 Begins run of 1s sub
1 1 Middle of run of 1s none
0 1 End of run of 1s add
0 0 Middle of run of 0s none
Originally for Speed (when shift was faster than add)
Replace a string of 1s in multiplier with an initial subtract when we first see a one and then later add for the bit after the last one –1
01111

19. Booths Example (2 x 7) Operation Multiplicand Product next?
0. initial value > sub
1a. P = P - m shift P (sign ext)
1b > nop, shift
> nop, shift
> add 4a
shift
4b done

20. Booths Example (2 x -3) Operation Multiplicand Product next?
0. initial value > sub
1a. P = P - m shift P (sign ext)
1b > add
2a shift P
2b > sub
3a shift
3b > nop
4a shift
4b done

21. Shifters
Two kinds:
logical-- value shifted in is always "0"
arithmetic-- on right shifts, sign extend
"0"
msb
lsb
"0"
msb
lsb
"0"
Note: these are single bit shifts. A given instruction might request 0 to 32 bits to be shifted!

22. Combinational Shifter from MUXes
Basic Building Block 1
sel
2-to-1 Mux D
8-bit right shifter 1
S2 S1 S0 A0 A1 A2 A3 A4 A5 A6 A7 R0 R1 R2 R3 R4 R5 R6 R7
What comes in the MSBs?
How many levels for 32-bit shifter?

23. Unsigned Divide: Paper & Pencil
1001 Quotient
Divisor Dividend – – Remainder (or Modulo result)
See how big a number can be subtracted, creating quotient bit on each step
Binary => 1 * divisor or 0 * divisor
Dividend = Quotient x Divisor + Remainder
3 versions of divide, successive refinement

24. DIVIDE HARDWARE Version 1
64-bit Divisor reg, 64-bit ALU, 64-bit Remainder reg, 32-bit Quotient reg
Shift Right
Divisor
64 bits
Quotient
Shift Left
64-bit ALU
32 bits
Write
Remainder
Control
64 bits

25. Divide Algorithm Version 1
Start: Place Dividend in Remainder
Divide Algorithm Version 1
Takes n+1 steps for n-bit Quotient & Rem.
Remainder Quotient Divisor
1. Subtract the Divisor register from the
Remainder register, and place the result
in the Remainder register.
Remainder  0
Test Remainder
Remainder < 0
2a. Shift the
Quotient register
to the left setting
the new rightmost
bit to 1.
2b. Restore the original value by adding the
Divisor register to the Remainder register, &
place the sum in the Remainder register. Also
shift the Quotient register to the left, setting
the new least significant bit to 0.
Q: 0000 D: R: –D =
1: R = R–D Q: 0000 D: R:
2b: +D, sl Q, 0 Q: 0000 D: R:
3: Shr D Q: 0000 D: R: –D =
1: R = R–D Q: 0000 D: R:
2b: +D, sl Q, 0 Q: 0000 D: R:
3: Shr D Q: 0000 D: R: –D =
1: R = R–D Q: 0000 D: R:
2b: +D, sl Q, 0 Q: 0000 D: R:
3: Shr D Q: 0000 D: R: –D =
1: R = R–D Q: 0000 D: R:
2a: sl Q, 1 Q: 0001 D: R:
3: Shr D Q: 0000 D: R: –D =
1: R = R–D Q: 0000 D: R:
2a: sl Q, 1 Q: 0011 D: R:
3: Shr D Q: 0011 D: R:
Recommend show 2’s comp of divisor, show lines for subtract divisor and restore remainder
3. Shift the Divisor register right 1 bit.
n+1
repetition?
No: < n+1 repetitions
Yes: n+1 repetitions (n = 4 here)
Done

26. Observations on Divide Version 1
1/2 bits in divisor always 0 => 1/2 of 64-bit adder is wasted => 1/2 of divisor is wasted
Instead of shifting divisor to right, shift remainder to left?
1st step cannot produce a 1 in quotient bit (otherwise too big) => switch order to shift first and then subtract, can save 1 iteration

27. Divide: Paper & Pencil
Quotient
Divisor Dividend – – Remainder (or Modulo result)
Notice that there is no way to get a 1 in leading digit! (this would be an overflow, since quotient would have n+1 bits)

28. DIVIDE HARDWARE Version 2
32-bit Divisor reg, 32-bit ALU, 64-bit Remainder reg, 32-bit Quotient reg
Divisor
32 bits
Quotient
Shift Left
32-bit ALU
32 bits
Shift Left
Remainder
Control
64 bits
Write

29. Divide Algorithm Version 2
Start: Place Dividend in Remainder
Divide Algorithm Version 2
Remainder Quotient Divisor
1. Shift the Remainder register left 1 bit.
2. Subtract the Divisor register from the left half of the Remainder register, & place the
result in the left half of the Remainder register.
Remainder 0
Test Remainder
Remainder < 0
Q: 0000 D: 0010 R:
1: Shl R Q: 0000 D: 0010 R:
2: R = R–D Q: 0000 D: 0010 R:
3b: +D, sl Q, 0 Q: 0000 D: 0010 R:
1: Shl R Q: 0000 D: 0010 R:
2: R = R–D Q: 0000 D: 0010 R:
3b: +D, sl Q, 0 Q: 0000 D: 0010 R:
1: Shl R Q: 0000 D: 0010 R:
2: R = R–D Q: 0000 D: 0010 R:
3a: sl Q, 1 Q: 0001 D: 0010 R:
1: Shl R Q: 0000 D: 0010 R:
2: R = R–D Q: 0000 D: 0010 R:
3a: sl Q, 1 Q: D: 0010 R:
3a. Shift the
Quotient register
to the left setting
the new rightmost
bit to 1.
3b. Restore the original value by adding the Divisor
register to the left half of the Remainderregister,
&place the sum in the left half of the Remainder
register. Also shift the Quotient register to the left,
setting the new least significant bit to 0.
nth
repetition?
No: < n repetitions
Yes: n repetitions (n = 4 here)
Done

30. Observations on Divide Version 2
Eliminate Quotient register by combining with Remainder as shifted left
Start by shifting the Remainder left as before.
Thereafter loop contains only two steps because the shifting of the Remainder register shifts both the remainder in the left half and the quotient in the right half
The consequence of combining the two registers together and the new order of the operations in the loop is that the remainder will shifted left one time too many.
Thus the final correction step must shift back only the remainder in the left half of the register

31. DIVIDE HARDWARE Version 3
32-bit Divisor reg, 32 -bit ALU, 64-bit Remainder reg, (0-bit Quotient reg)
Divisor
32 bits
32-bit ALU
“HI”
“LO”
Shift Left
Remainder
(Quotient)
Control
64 bits
Write

32. Divide Algorithm Version 3
Start: Place Dividend in Remainder
Divide Algorithm Version 3
Remainder Divisor
1. Shift the Remainder register left 1 bit.
2. Subtract the Divisor register from the left half of the Remainder register, & place the
result in the left half of the Remainder register.
Remainder  0
Test Remainder
Remainder < 0
D: 0010 R:
0: Shl R D: 0010 R:
1: R = R–D D: 0010 R:
2b: +D, sl R, 0 D: 0010 R:
1: R = R–D D: 0010 R:
2b: +D, sl R, 0 D: 0010 R:
1: R = R–D D: 0010 R:
2a: sl R, 1 D: 0010 R:
1: R = R–D D: 0010 R:
2a: sl R, 1 D: 0010 R:
Shr R(rh) D: 0010 R:
3a. Shift the
Remainder register
to the left setting
the new rightmost
bit to 1.
3b. Restore the original value by adding the Divisor
register to the left half of the Remainderregister,
&place the sum in the left half of the Remainder
register. Also shift the Remainder register to the
left, setting the new least significant bit to 0.
nth
repetition?
No: < n repetitions
Yes: n repetitions (n = 4 here)
Done. Shift left half of Remainder right 1 bit.

33. Observations on Divide Version 3
Same Hardware as Multiply: just need ALU to add or subtract, and 63-bit register to shift left or shift right
Hi and Lo registers in MIPS combine to act as 64-bit register for multiply and divide
Signed Divides: Simplest is to remember signs, make positive, and complement quotient and remainder if necessary
Note: Dividend and Remainder must have same sign
Note: Quotient negated if Divisor sign & Dividend sign disagree e.g., –7 ÷ 2 = –3, remainder = –1
Possible for quotient to be too large: if divide 64-bit interger by 1, quotient is 64 bit