1. EXECUTION OF COMPLETE INSTRUCTION

2. Overview
Instruction Set Processor (ISP):processing unit executes machine instruction and coordinate the activities of other units
Central Processing Unit (CPU):examine internal structure and how it performs the task of fetching,decoding, and executing instructions of a program
A typical computing task consists of a series of steps specified by a sequence of machine instructions that constitute a program.
An instruction is executed by carrying out a sequence of more operations.

3. Some Fundamental Concepts

4. Fundamental Concepts
Processor fetches one instruction at a time and perform the operation specified.
Instructions are fetched from successive memory locations until a branch or a jump instruction is encountered.
Processor keeps track of the address of the memory location containing the next instruction to be fetched using Program Counter (PC).
Instruction Register (IR)

5. Fundamental Concepts- To Execute an Instruction,processor involve 3 steps
1.Fetch the contents of the memory location pointed to by the PC. The contents of this location are loaded into the IR (fetch phase).
IR ← [[PC]]
2.Assuming that the memory is byte addressable, increment the contents of the PC by 4 (fetch phase).
PC ← [PC] + 4

6. 3.Carry out the actions specified by the instruction in the IR

7. Processor Organization
MDR HAS TWO INPUTS AND TWO OUTPUTS
Datapath
Textbook Page 413

8. Fundamental Concepts MDR-2 I/P & 2 O/P
MAR- I/P from internal bus and o/p is connected to external bus
Data bus & address bus line are connected to internal processor bus via MDR &MAR
Control line of memory bus are connected to instruction decoder and control logic block and it is responsible for issuing signal that control all the units

9. Fundamental Concepts
Three register Y,Z,TEMP are temporary register used by processor for temporary storage during execution
These 3 registers are never used for storing data for future reference
MUX(multiplexer) selects either o/p of register Y or a constant value 4 to provide as i/p to ALU

10. Fundamental Concepts
Data are transferred from one register to another register via ALU
Instruction decoder and control logic unit is responsible for implementing action specified by instruction loaded in IR
Decoder generate ctrl signal to select register involved & direct the transfer of data
Register,ALU & interconnectcng bus are collectively referred as Datapath

11. Fundamental Concepts Instruction execution Operation:-
Transfer a word of data from one processor register to another or to the ALU.
Perform an arithmetic or a logic operation and store the result in a processor register.
Fetch the contents of a given memory location and load them into a processor register.
Store a word of data from a processor register into a given memory location.

12. Register Transfers

13. Register Transfers B A Z
ALU Y in
out R i b us
Internal processor
Constant 4
MUX
Figure Input and output gating for the registers in Figure 7.1.
Select

14. Register Transfers
I/p & o/p of register Ri are connected to bus via switches controlled by signals Ri in & Ri out
When Ri in is set to 1,the data on the bus are loaded to Ri
When Ri out is set to 1,content of register Ri are placed on the bus

15. Register Transfers Transfer the content of register R1 to R4
(2 bulletin points in pg-415)
refer from book
All operations and data transfer within the processor takes place within time periods is defined by processor clock
Data transfer may use both rising & falling edges of the clock
When edge triggered flip flop are not used, 2

16. Register Transfers
or more clock signal may be needed to guarantee proper transfer of data,known as multiphase clocking
Figure Input and output gating for one register bit(explaination refer book pg -415 ( 4th & 5th para))

17. Figure 7.3. Input and output gating for one register bit.
Register Transfers
All operations and data transfers are controlled by the processor clock.
Figure Input and output gating for one register bit.

18. Performing an Arithmetic or Logic Operation

19. Performing an Arithmetic or Logic Operation
The ALU is a combinational circuit that has no internal storage.
ALU gets the two operands from MUX and bus. The result is temporarily stored in register Z.
What is the sequence of operations to add the contents of register R1 to those of R2 and store the result in R3?
R1out, Yin
R2out, SelectY, Add, Zin
Zout, R3in
explaination refer book pg -417 ( 2nd para))

20. Fetching a Word from Memory

21. Fetching a Word from Memory
Address into MAR; issue Read operation; data into MDR.
Figure Connection and control signals for register MDR.

22. MDR in and MDR out control connection to the internal bus
MDR inE and MDR outE control connection to the external bus
MDR inE = 1,i/p is selected from memory bus
A second tri- state gate controlled by MDR out E used to connect output of the flip flop to memory bus

23. Processor completes one internal data transfer in one clock cycle
Cache will respond to memory read request in one clock cycle
When cache miss occur request is forwarded to main memory
the processor waits until it receives an indication that the requested operation has been completed (Memory-Function-Completed, MFC).

24. Fetching a Word from Memory
WMFC is the control signal that cause the processor’s control circuit to wait for the arrival of MFC signal
Example of READ opeartion:
How to Move (R1), R2?
MAR ← [R1]
Start a Read operation on the memory bus
Wait for the MFC response from the memory
Load into MDR from the memory bus
R2 ← [MDR]

25. MAR ← [R1]
Start a Read operation on the memory bus
Wait for the MFC response from the memory
Load MDR from the memory bus
R2 ← [MDR]
R1 out , MAR in ,Read
MDR inE, WMFC
MDR out, R2 in

26. STORING A WAORD IN MEMORY
MOVE R2,(R1)
R1 out , MAR in
R2 out , MDR in ,Write
MDR outE, WMFC
Desired address(R1) is loaded into MAR
Data to be written are loaded into MDR & Write command is issued
explaination refer book pg -420( last para))

27. Execution of a Complete Instruction
Add (R3), R1
Fetch the instruction
Fetch the first operand (the contents of the memory location pointed to by R3)
Perform the addition
Load the result into R1

28. Architecture B A Z
ALU Y in
out R i b us
Internal processor
Constant 4
MUX
Figure Input and output gating for the registers in Figure 7.1.
Select

29. Execution of a Complete Instruction
Add (R3), R1

30. Execution of Branch Instructions
A branch instruction replaces the contents of PC with the branch target address, which is usually obtained by adding an offset X given in the branch instruction.
The offset X is usually the difference between the branch target address and the address immediately following the branch instruction.
Conditional branch

31. Execution of Branch Instructions
Step
Action 1 PC ,
MAR ,
Read,
Select4,
Add, Z
out in in 2 Z , PC , Y ,
WMF C
out in in 3
MDR , IR
out in 4
Offset-field-of-IR ,
Add, Z
out in 5 Z , PC ,
End
out in
Figure Control sequence for an unconditional branch instruction.

32. Hardwired Control

33. Overview
To execute instructions, the processor must have some means of generating the control signals needed in the proper sequence.
Two categories: hardwired control and microprogrammed control
Hardwired system can operate at high speed; but with little flexibility.

34. Control Unit Organization
CLK
Control step
Clock
counter
External
inputs
Decoder/ IR
encoder
Condition
codes
Control signals
Figure Control unit organization.

35. Detailed Block Description

36. Generating Zin Zin = T1 + T6 • ADD + T4 • BR + …
Branch
Add T T 4 6 T 1
Figure Generation of the Zin control signal for the processor in Figure 7.1.

37. A Complete Processor