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ELEC 5270 – Low Power Design of Electronic Circuits Spring 2009 Grant Lewis 1.

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Presentation on theme: "ELEC 5270 – Low Power Design of Electronic Circuits Spring 2009 Grant Lewis 1."— Presentation transcript:

1 ELEC 5270 – Low Power Design of Electronic Circuits Spring 2009 Grant Lewis 1

2  3-bit Counter has 14 transitions in 8 cycles  14/8 = 1.75 transitions per cycle  N-bit Counter has 2(2 N -1) transitions  Transitions per cycle → 2 as N→ ∞ 4-bit 1.875 transitions/clock 5-bit 1.9375 6-bit 1.96875 7-bit 1.984375 8-bit 1.9921875 9-bit 1.99609375 000-- 0011 0102 0111 1003 1011 1102 1111 0003 2

3  A =  B =  C =  8 logic gates Synthesize in Leonardo Spectrum 3

4  3-bit counter has 8 transitions in 8 cycles  8/8 = 1 transition per cycle  N-bit counter has 2 N transitions  Transitions per cycle is 1 for any size counter  For large counters, ratio of transitions for Decimal to Gray → 2 000-- 0011 0111 0101 1101 1111 1011 1001 0001 4

5  Gray Encoding can be accomplished by  Binary to Gray conversion  Directly Synthesizing Gray Counter  Binary to Gray conversion is accomplished with 2 XOR gates 5

6  With optimizations, adds one logic gate (total 9 logic gates) 6

7  A =  B =  C =  Adds 4 logic gates (total 12 gates) 7

8  Power analysis conducted with powersim.18 μm, 1.8V supply 8 Decimal Encoding Decimal to Gray % Reduction Gray Encoding % Reduction # of Gates89-12.5%12-50% # of Glitches31223496-11.97%161848.17% Glitch Power (μW)1.8523071.583410 14.52%0.93429749.56% Dynamic Power (μW) 1.8551271.58736414.43% 0.94032049.31% Leakage Power (μW).914450.986150-7.84%.8895972.72% Logic Power (μW).002820.003955-40.25%.006024-113.62% Total Power (μW)2.769578 2.573515 7.08%1.82991834.18%

9  Much of dynamic power consumption comes from glitches  Can be reduced by path balancing  Directly implementing gray counter in logic removes ~1/2 of the glitches, however consumes more leakage and logic power due to increase in number of logic gates  Overall, gray counters are more power efficient 9

10  Hakenes, R.; Manoli Y. “A Segmented Gray Code for Low-Power Microcontroller Address Buses”. EUROMICRO Conference, 1999. Proceedings. 25 th, Pages 240 – 243, Vol. 1  Doran, R. W. “The Gray Code”. Centre for Discrete Mathematics and Theoretical Computer Science, March, 2007.  Mehta, Huzefa et al. “Some Issues in Gray Code Addressing”. Proceedings of the 6th Great Lakes Symposium on VLSI, 1996. Pages 178 – 181. 10


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