1. 7.4.05-1 Integrated Circuits and Systems Laboratory Darmstadt University of Technology Design Space Exploration of incompletely specified Embedded Systems by Genetic Algorithm Stephan Klaus Ralf Laue Sorin Alexander Huss Integrated Circuits and System Laboratory Department of Computer Science Technische Universität Darmstadt Germany

2. 7.4.05-2 Outline Motivation Specification Model Genetic Design Space Exploration Application Example Conclusion

3. 7.4.05-3 Motivation Embedded Systems Real-time and costs requirements Different areas of application Growing complexity Shorter design cycles System Level Design Determine needed tasks Determine suited architecture Map complex tasks to architecture Implementation consists of: Allocation, Binding, Scheduling Embedded Systems are no longer designed from scratch, but partly from existing modules

4. 7.4.05-4 Incomplete Specifications Design Process with unknown execution properties necessary Determine maximal execution times for new modules considering deadlines and known modules The implementation of new modules can take place according to the determined maximal execution times Implementation consisting of already existing modules (known execution properties) a few custom made modules (unknown execution properties: no runtime estimations possible before HW/SW design decisions)

5. 7.4.05-5 Design Space Exploration Goal: Determine suited implementation alternatives considering latency and costs Multi-Objective Optimization Problem Objective 1 Objective 2 Solution Pareto Front

6. 7.4.05-6 Specification Model Hierarchical CoDesign Model (hCDM) Hierarchical Task Graph Structure Data and Control- flow Information Condition captures control-flow normal join fork c=false c=true

7. 7.4.05-7 Genetic Algorithm genetic Algorithm System Level Synthesis with genetic Algorithm Multi-objective optimization Suited for large and non-convex search spaces Considers sets of solutions No linear cost function necessary One-pass optimisation Initialize population Select individuals Crossover individuals Mutate individuals Stop criteria finish set of Pareto optimal implementation alternatives maximal execution times for new modules. Determines a set of Pareto optimal implementation alternatives (allocation, binding, schedule) alternatives including maximal execution times for new modules. Evaluate individuals

8. 7.4.05-8 Genetic Representation AllocationBindingScheduleExec. Times PurposeDetermine set of resources Assign a resource to each task Assign a priority to each task Determine execution times Example Repre- sentation R1, R3, … T1T2…TnT1T2…TnT1T4 R3R1… 4n…115070 Mutation Operations Remove/Add resources Select another resource from the allocation Exchange priorities Add/Sub time value Crossover Operations Mix resources from both parent sets Mix bindings from both parents Mix priorities from both parents Mix time values from both parents

9. 7.4.05-9 Evaluation Pareto ranking To perform Pareto ranking of all goals: Determine latency, cost and sum of maximal new execution times Objectives: fulfill deadlines and minimize costs and maximize sum of execution times Each Individual is rated by the amount of individuals which are dominated by it The individuals with the highest values are preferred

10. 7.4.05-10 Timing Evaluation 1: while ReadySet not empty do 2: io = Find IO Rel. with highest priority 3: if New Control Path in io then 4: Spilt ReadSet according to new condition 5: Duplicate schedule 6: EvalTiming(ReadySet1, FinishedSet, c1) 7: EvalTiming(ReadySet2, FinishedSet, c2) 8: else 9: ReadySet erase io; FinishedSet insert io 10: Calculate earliest start time ts of io 11: if new task with unknown timing then 12: texec = Get timing of io from individual 13: else 14: texec = Get timing of io from resource 15: Schedule insert (io, ts, ts + texec,Cond) 16: ReadySet insert ready tasks 17: end if 18: end while

11. 7.4.05-11 Application Example Mobile Robot equipped with an optical navigation Overall deadline: 420ms

12. 7.4.05-12 First Implementation 0100200300400 time US mC PC PCI RS232 FPGA Dist GUIPicPathGUI MotorReg CaStop Reg (c,F) (c,T) (c,F) (c,T) Pos

13. 7.4.05-13 Second Implementation 0100200300400 time US mC PC PCI RS232 FPGA Dist GUI Pic Motor Path Reg Stop (c,F) (c,T) (c,F) (c,T) Path GUI Ca GUI (c,F) (c,T) New Module: Pos

14. 7.4.05-14 Conclusion System Level Design Space Exploration by genetic Algorithm: Determines complete implementation alternatives (consisting of Allocation, Binding, Scheduling) Considers incomplete specifications Considers incomplete specifications Advantages: No estimation of unknown execution times necessary Maximal execution times for new modules Leads to easier implementation of such modules

15. 7.4.05-15 Integrated Circuits and Systems Laboratory Darmstadt University of Technology Stephan Klaus Ralf Laue Sorin Alexander Huss www.vlsi.informatik.tu-darmstadt.de klaus|laue|huss@iss.tu-darmstadt.de Design Space Exploration of incompletely specified Embedded Systems by Genetic Algorithm