1. Computer Architecture and Organization Unit -3 Instruction Set Architecture

2. Table Of contents Instruction based classification of computers: RISC and CISC Addressing modes Operations in the instruction set Simulation using MASM

3. Instruction Format Instruction Fields : opcode field – specify the operations to be performed Address field(s) – designate memory address(es) or processor register(s) Mode field(s) – determine how the address field is to be interpreted to get effective address or the operand The number of address fields in the instr format : depend on the internal organization of CPU The three most common CPU organizations : - Single accumulator organization : ADD X /* AC ← AC + M[X] */ - General register organization : ADD R1, R2, R3 /* R1 ← R2 + R3 */ ADD R1, R2 /* R1 ← R1 + R2 */ MOV R1, R2 /* R1 ← R2 */ ADD R1, X /* R1 ← R1 + M[X] */ - Stack organization : PUSH X /* TOS ← M[X] */ ADD

4. Three-, Two-address Instructions Three-address Instructions - Program to evaluate X = (A + B) * (C + D) : ADD R1, A, B /* R1 ← M[A] + M[B] */ ADD R2, C, D /* R2 ← M[C] + M[D] */ MUL X, R1, R2 /* M[X] ← R1 * R2 */ - Results in short program - Instruction becomes long (many bits) Two-address Instructions - Program to evaluate X = (A + B) * (C + D) : MOV R1, A /* R1 ← M[A] */ ADD R1, B /* R1 ← R1 + M[A] */ MOV R2, C /* R2 ← M[C] */ ADD R2, D /* R2 ← R2 + M[D] */ MUL R1, R2 /* R1 ← R1 * R2 */ MOV X, R1 /* M[X] ← R1 */

5. One-, Zero-address Instructions One-address Instructions - Use an implied AC register for all data manipulation - Program to evaluate X = (A + B) * (C + D) : LOAD A /* AC ← M[A] */ ADD B /* AC ← AC + M[B] */ STORE T /* M[T] ← AC */ LOAD C /* AC ← M[C] */ ADD D /* AC ← AC + M[D] */ MUL T /* AC ← AC * M[T] */ STORE X /* M[X] ← AC */

6. Zero-address Instructions - Can be found in a stack-organized computer - Program to evaluate X = (A + B) * (C + D) : PUSH A /* TOS ←A */ PUSH B /* TOS ←B */ ADD /* TOS ← (A + B) */ PUSH C /* TOS ←C */ PUSH D /* TOS ←D */ ADD /* TOS ← (C + D) */ MUL /* TOS ← (C + D) * (A + B) */ POP X /* M[X] ← TOS */

7. CISC(Complex Instruction Set Computer) These computers with many instructions and addressing modes came to be known as Complex Instruction Set Computers (CISC) One goal for CISC machines was to have a machine language instruction to match each high-level language statement type.

8. Summary: Criticisms on CISC - Complex Instruction → Format, Length, Addressing Modes → Complicated instruction cycle control due to the complex decoding HW and decoding process - Multiple memory cycle instructions → Operations on memory data → Multiple memory accesses/instruction - Microprogrammed control is necessity → Microprogram control storage takes substantial portion of CPU chip area → Semantic Gap is large between machine instruction and microinstruction - General purpose instruction set includes all the features required by individually different applications → When any one application is running, all the features required by the other applications are extra burden to the application

9. RISC In the late ‘70s - early ‘80s, there was a reaction to the shortcomings of the CISC style of processors – Reduced Instruction Set Computers (RISC) were proposed as an alternative The underlying idea behind RISC processors is to simplify the instruction set and reduce instruction execution time RISC processors often feature: – Few instructions – Few addressing modes – Only load and store instructions access memory – All other operations are done using on-processor registers – Fixed length instructions – Single cycle execution of instructions – The control unit is hardwired, not microprogrammed

10. RISC Cont… Since all (but the load and store instructions) use only registers for operands, – only a few addressing modes are needed By having all instructions the same length : – reading them in is easy and fast The fetch and decode stages are simple, looking much more like Mano’s BC than a CISC machine – The instruction and address formats are designed to be easy to decode – (Unlike the variable length CISC instructions,) the opcode and register fields of RISC instructions can be decoded simultaneously The control logic of a RISC processor is designed to be simple and fast : – The control logic is simple because of the small number of instructions and the simple addressing modes – The control logic is hardwired, rather than microprogrammed, because hardwired control is faster

11. Advantages of RISC VLSI Realization - Control area is considerably reduced ⇒ RISC chips allow a large number of registers on the chip - Enhancement of performance and HLL support -Higher regularization factor and lower VLSI design cost Computing Speed - Simpler, smaller control unit ⇒ faster - Simpler instruction set; addressing modes; instruction format ⇒ faster decoding - Register operation ⇒ faster than memory operation - Register window ⇒ enhances the overall speed of execution - Identical instruction length, One cycle instruction execution ⇒ suitable for pipelining ⇒ faster

12. Advantages of RISC’ Design Costs and Reliability - Shorter time to design ⇒ reduction in the overall design cost and reduces the problem that the end product will be obsolete by the time the design is completed -Simpler, smaller control unit ⇒ higher reliability - Simple instruction format (of fixed length) ⇒ ease of virtual memory management High Level Language Support -A single choice of instruction ⇒ shorter, simpler compiler - A large number of CPU registers ⇒ more efficient code - Register window ⇒ Direct support of HLL - Reduced burden on compiler writer

13. RISC vs CISC The CISC Approach Thus, the entire task of multiplying two numbers can be completed with one instruction: –MULT 2:3, 5:2 One of the primary advantages of this system is that the compiler has to do very little work to translate a high- level language statement into assembly. Because the length of the code is relatively short, very little RAM is required to store instructions. The emphasis is put on building complex instructions directly into the hardware.

14. The RISC Approach In order to perform the exact series of steps described in the CISC approach, a programmer would need to code four lines of assembly: –LOAD A, 2:3 LOAD B, 5:2 PROD A, B STORE 2:3, A At first, this may seem like a much less efficient way of completing the operation. Because there are more lines of code, more RAM is needed to store the assembly level instructions. The compiler must also perform more work to convert a high-level language.

15. RISC vs CISC Emphasis on hardware Transistors used for storing complex instructions Emphasis on software Spends more transistors on memory registers Includes multi-clock complex instructions, Single-clock reduced instruction only Memory-to-memory: "LOAD" and "STORE" incorporated in instructions Register to register: "LOAD" and "STORE" are independent instructions Small code sizeslarge code sizes high cycles per secondLow cycles per second

16. Addressing Modes * Specifies a rule for interpreting or modifying the address field of the instruction (before the operand is actually referenced) * Variety of addressing modes - to give programming flexibility to the user - to use the bits in the address field of the instruction efficiently

17. Types of Addressing Modes Implied Mode : Address of the operands are specified implicitly in the definition of the instruction - No need to specify address in the instruction - EA = AC, or EA = Stack[SP] - Examples from BC : CLA, CME, INP Immediate Mode : Instead of specifying the address of the operand,operand itself is specified - No need to specify address in the instruction - However, operand itself needs to be specified - (-)Sometimes, require more bits than the address - (+) Fast to acquire an operand - Useful for initializing registers to a constant value

18. Type of Addressing Modes- Cont.. Register Mode : Address specified in the instruction is the register address - Designated operand need to be in a register - (+) Shorter address than the memory address -- Saving address field in the instruction - (+) Faster to acquire an operand than the memory addressing - EA = IR(R) (IR(R): Register field of IR) Register Indirect Mode : Instruction specifies a register which contains the memory address of the operand - (+) Saving instruction bits since register address is shorter than the memory address - (-) Slower to acquire an operand than both the register addressing or memory addressing - EA = [IR(R)] ([x]: Content of x) Autoincrement or Autodecrement Mode - Similar to the register indirect mode except : When the address in the register is used to access memory, the value in the register is incremented or decremented by 1 automatically

19. Type of Addressing Modes- Cont.. Direct Address Mode : Instruction specifies the memory address which can be used directly to access the memory - (+) Faster than the other memory addressing modes - (-) Too many bits are needed to specify the address for a large physical memory space - EA = IR(addr) (IR(addr): address field of IR) - E.g., the address field in a branch-type instr Indirect Addressing Mode : The address field of an instruction specifies the address of a memory location that contains the address of the operand - (-) Slow to acquire an operand because of an additional memory access - EA = M[IR(address)]

20. Type of Addressing Modes- Cont.. Relative Addressing Modes : The Address fields of an instruction specifies the part of the address (abbreviated address) which can be used along with a designated register to calculate the address of the operand --> Effective addr = addr part of the instr + content of a special register - (+) Large physical memory can be accessed with a small number of address bits - EA = f(IR(address), R), R is sometimes implied --> Typically EA = IR(address) + R - 3 different Relative Addressing Modes depending on R * (PC) Relative Addressing Mode (R = PC) * Indexed Addressing Mode (R = IX, where IX: Index Register) * Base Register Addressing Mode (R = BAR(Base Addr Register)) * Indexed addressing mode vs. Base register addressing mode - IR(address) (addr field of instr) : base address vs. displacement - R (index/base register) : displacement vs. base address - Difference: the way they are used (NOT the way they are computed) * indexed addressing mode : processing many operands in an array using the same instruction. * base register addressing mode : facilitate the relocation of programs in memory in multiprogramming systems

21. Addressing Modes: Examples

22. DATA TRANSFER INSTRUCTIONS Load LD Store ST Move MOV Exchange XCH Input IN Output OUT Push PUSH Pop POP Name Mnemonic Typical Data Transfer Instructions Direct addressLD ADRAC  M[ADR] Indirect addressLD @ADRAC  M[M[ADR]] Relative addressLD $ADRAC  M[PC + ADR] Immediate operandLD #NBRAC  NBR Index addressingLD ADR(X)AC  M[ADR + XR] RegisterLD R1AC  R1 Register indirectLD (R1)AC  M[R1] AutoincrementLD (R1)+AC  M[R1], R1  R1 + 1 Autodecrement LD -(R1) R1  R1 - 1, AC  M[R1] Mode Assembly Convention Register Transfer Data Transfer and Manipulation Data Transfer Instructions with Different Addressing Modes

23. DATA MANIPULATION INSTRUCTIONS Three Basic Types: Arithmetic instructions Logical and bit manipulation instructions Shift instructions Arithmetic Instructions Name Mnemonic ClearCLR ComplementCOMANDOR Exclusive-ORXOR Clear carryCLRC Set carrySETC Complement carryCOMC Enable interruptEI Disable interruptDI Name Mnemonic Logical shift rightSHR Logical shift leftSHL Arithmetic shift rightSHRA Arithmetic shift leftSHLA Rotate rightROR Rotate leftROL Rotate right thru carryRORC Rotate left thru carryROLC Name Mnemonic Logical and Bit Manipulation Instructions Shift Instructions Data Transfer and Manipulation Increment INC Decrement DEC Add ADD Subtract SUB Multiply MUL Divide DIV Add with Carry ADDC Subtract with Borrow SUBB Negate(2’s Complement) NEG

24. PROGRAM CONTROL INSTRUCTIONS Program Control PC +1 In-Line Sequencing (Next instruction is fetched from the next adjacent location in the memory) Address from other source; Current Instruction, Stack, etc; Branch, Conditional Branch, Subroutine, etc Program Control Instructions Name Mnemonic Branch BR Jump JMP Skip SKP Call CALL Return RTN Compare(by  ) CMP Test(by AND) TST * CMP and TST instructions do not retain their results of operations (  and AND, respectively). They only set or clear certain Flags.

25. CONDITIONAL BRANCH INSTRUCTIONS BZBranch if zeroZ = 1 BNZBranch if not zeroZ = 0 BCBranch if carryC = 1 BNCBranch if no carryC = 0 BPBranch if plusS = 0 BMBranch if minusS = 1 BVBranch if overflowV = 1 BNVBranch if no overflowV = 0 BHIBranch if higherA > B BHEBranch if higher or equalA  B BLOBranch if lowerA < B BLOEBranch if lower or equalA  B BEBranch if equalA = B BNEBranch if not equalA  B BGTBranch if greater thanA > B BGEBranch if greater or equalA  B BLTBranch if less thanA < B BLEBranch if less or equalA  B BEBranch if equalA = B BNEBranch if not equalA  B Unsigned compare conditions (A - B) Signed compare conditions (A - B) Mnemonic Branch condition Tested condition Program Control

26. SUBROUTINE CALL AND RETURN Call subroutine Jump to subroutine Branch to subroutine Branch and save return address Fixed Location in the subroutine (Memory) Fixed Location in memory In a processor Register In memory stack - most efficient way Program Control Subroutine Call Two Most Important Operations are Implied; * Branch to the beginning of the Subroutine - Same as the Branch or Conditional Branch * Save the Return Address to get the address of the location in the Calling Program upon exit from the Subroutine Locations for storing Return Address CALL SP  SP - 1 M[SP]  PC PC  EA RTN PC  M[SP] SP  SP + 1

27. PROGRAM INTERRUPT Types of Interrupts External interrupts External Interrupts initiated from the outside of CPU and Memory - I/O Device → Data transfer request or Data transfer complete - Timing Device → Timeout - Power Failure - Operator Internal interrupts (traps) Internal Interrupts are caused by the currently running program - Register, Stack Overflow - Divide by zero - OP-code Violation - Protection Violation Software Interrupts Both External and Internal Interrupts are initiated by the computer HW. Software Interrupts are initiated by the executing an instruction. - Supervisor Call → Switching from a user mode to the supervisor mode → Allows to execute a certain class of operations which are not allowed in the user mode Program Control

28. MASM The name MASM originally referred to MACRO ASSEMBLER but over the years it has become synonymous with Microsoft Assembler. An assembly language translator that converts macros into several machine language instructions. MASM isn't the fastest assembler around (it's not particularly slow, except in a couple of degenerate cases, but there are faster assemblers available). Though very powerful, there are a couple of assemblers that, arguably, are more powerful (e.g., TASM and HLA). MASM is only usable for creating DOS and Windows applications; you cannot effectively use it to create software for other operating systems.

29. Benefits of MASM Still, there are some benefits to using MASM today: –Steve Hutchessen's ("Hutch") MASM32 package provides the support for MASM that Microsoft no longer provides. –You can download MASM (and MASM32) free from Microsoft and other sites. –Most Windows' assembly language examples on the Internet today use MASM syntax. –You may download MASM directly from Webster as part of the MASM32 package.