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Chapter # 8 Figure 8-1 Major components of CPU Control Register Set [ Register Set [ Arithmetic Logic unit (ALU) [ Arithmetic Logic unit (ALU) [

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Chapter # 8 Figure 8-2 Register set with common ALU R1 R2 R3 R4 R5 R6 R7 MUX INPUT Arithmetic logic unit (ALU) OPR SELA SELB 3 X 8 decoder output

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Chapter # 8 Table 8-1 Encoding of Register Selection Fields. Binary CodeSELASELBSELD 000InputInputNone 001R1R1R1 010R2R2R2 011R3R3R3 100R4R4R4 101R5R5R5 110R6R6R6 111R7R7R7

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Chapter # 8 Table 8-2 Encoding of ALU operations. OPR SelectOperationSymbol 00000Transfer ATSFA 00001Increment AINCA 00010Add A + BADD 00101Subtract A – BSUB 00110Decrement ADECA 01000AND A and BAND 01010OR A and BOR 01100XOR A and BXOR 01110Complement ACOMA 10000Shift right ASHRA 11000Shift left ASHLA

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Chapter # 8 Binary Code for Subtract Micro operation. Field:SELASELBSELDOPR Symbol:R2R3R1SUB Control Word R1 R2 – R3

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Chapter # 8 Table 8-3 Examples of Micro operations for the CPU. Symbolic Designation Micro operationSELASELBSELDOPR Control Word R1 R2 – R3R2R3R1SUB R4 R4 R5R4R5R4OR R6 R6 + 1R6-R6INCA R7 R1R1-R7TSFA Output R2R2-NoneTSFA Output InputInput-NoneTSFA R4 shl R4R4-R4SHLA R5 0R5R5R5XOR

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Chapter # 8 Figure 8-3 Block Diagram of a 64-word stack. FULLEMTY A B C SP DR Address

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Chapter # 8 Push and Pop Micro operations Push SP SP + 1Increment stack pointer M[SP] DRWrite item on top of the stack If (SP = 0) then (FULL 1)Check if stack is full EMTY 0Mark the stack not empty Pop DR M[SP]Read item from the top of stack SP SP – 1Decrement stack pointer If (SP = 0) then (EMTY 1)Check if stack is empty FULL 0Mark the stack not Full

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Chapter # 8 Figure 8-4 Computer memory with program, data, and stack segments. Memory Unit SP AR PC DR

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Chapter # 8 Figure 8-5 Stack operations to evaluate

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Chapter # 8 The most common fields in instruction formats 1. An operation code field that specifies the operation to be performed. 2. An address field that designates a memory address or a processor register 3. A mode field that specifies the way the operand or the effective address is determined Three types of CPU organization 1. Single accumulator organization. 2. General register organization. 3. Stack organization.

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Chapter # 8 Three Address Instructions Expression: X= (A + B) * (C + D) Assembly language program. ADDR1, A, BR1 M[A] + M[B] ADDR2, C, DR2 M[C] + M[D] ADDX, R1, R2M[X] R1 * R2

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Chapter # 8 Two-Address Instructions Expression: X= (A + B) * (C + D) Assembly language program. MOVR1, AR1 M[A] ADDR1, BR1 R1 + M[B] MOVR2, CR2 M [C] ADD R2, DR2 R2 + M[D] MULR1, R2R1 R1 * R2 MOVX, R1M[X] R1

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Chapter # 8 One-Address Instructions Expression: X= (A + B) * (C + D) Assembly language program. LOADAAC M[A] ADDBAC AC + M[B] STORETM[T] AC LOAD CAC M[C] ADDDAC AC + M[D] MULTAC AC * M[T] STOREXM[X] AC

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Chapter # 8 Zero-Address Instruction. Expression: X= (A + B) * (C + D) Assembly language program. PUSHATOS A PUSHBTOS B ADDTOS (A + B ) PUSH CTOS C PUSHDTOS D ADDTOS (C + D) MULTOS (A + B)*(C + D) POPXM[X] TOS NOTE: TOS stands for top of stack

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Chapter # 8 RISC Instructions Expression: X= (A + B) * (C + D) Assembly language program. LOADR1, AR1 M[A] LOADR2, BR2 M[B] LOADR3, CR3 M[C] LOAD R4, DR4 M[D] ADDR1, R1,R2R1 R1+R2 ADDR3, R3,R2R3 R3+R4 MULR1, R1, R3R1 R1 * R3 STOREX,R1M[X] R1

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Chapter # 8 Addressing Modes 1.Implied Mode 2.Immediate Mode 3.Register Mode 4.Register Indirect Mode 5.Auto increment or Auto decrement Mode 6.Direct Address Mode 7.Indirect Address Mode 8.Relative Address Mode 9.Indexed Addressing Mode 10.Base Register Addressing Mode

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Chapter # 8 Figure 8-7 Numerical example for addressing modes Mode Load to AC Address = 500 Next instruction PC=200 R1=400 XR= 100 AC MemoryAddress

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Chapter # 8 Table 8-4 Tabular List of Numerical Example Addressing ModeEffective AddressContent of AC Direct Address Immediate operand Indirect Address Relative Address Indexed Address Register-400 Register Indirect Auto increment Auto decrement399450

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Chapter # 8 Table 8-5 Typical Data Transfer Instructions. NameMnemonic LoadLD StoreST MoveMOV ExchangeXCH InputIN OutputOUT PushPUSH PopPOP

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Chapter # 8 Table 8-6 Eight Addressing Modes for the Load Instruction. Assembly Mode ConventionRegister Transfer Direct addressLD ADRAC M[ADR] Indirect M[M [ADR] ] Register relativeLD $ADRAC M[PC + ADR] Immediate operandLD # NBRAC NBR Index addressingLD ADR(X)AC M[ADR + XR] RegisterLD R1AC R1 Register indirectLD (R1)AC M[R1] Auto incrementLD (R1)+AC M[R1], R1 R1 + 1

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Chapter # 8 Table 8-7 Typical Arithmetic instructions NameMnemonic IncrementINC DecrementDEC AddADD SubtractSUB MultiplyMUL DivideDIV Add with carryADDC Subtract with borrowSUBB Negate(2’s Comp )NEG

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Chapter # 8 Table 8-8 Typical Logical and Bit Manipulation Instructions. NameMnemonic ClearCLR ComplementCOMANDOR Exclusive-ORXOR Clear carryCLRC Set carrySETC Complement carryCOMC Enable interruptEI Disable interruptDI

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Chapter # 8 Table 8-9 Typical Shift Instructions NameMnemonic Logical shift rightSHR Logical shift leftSHL Arithmetic shift rightSHRA Arithmetic shift leftSHRL Rotate rightROR Rotate leftROL Rotate right through carryRORC Rotate left through carry ROLC

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Chapter # 8 Table 8-9 Typical Program Control Instructions NameMnemonic BranchBR JumpJMP SkipSKP CallCALL ReturnRET Compare (by subtraction)CMP Test (by ANDing)TST

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Chapter # 8 Shift Bit Conditions. Bit C (carry) is set to 1 if the end carry C 8 is 1. It is cleared to 0 if the carry is 0. Bit S (sign) is set to 1 if the highest-order bit F 7 is 1. It is set to 0 if the bit is 0. Bit Z (zero) is set to 1 if the output of ALU contains all 0’s. It is cleared to 0 otherwise. In other words, Z=1 if the out put is zero and Z=0 if the output is not zero. Bit V (overflow) is set to 1 if the exclusive-OR of the last two carries is equal to 1, and cleared to 0 otherwise. This is the condition for an overflow when negative number are in 2’s complement. For the 8-bit ALU, V=1 if the output is greater than +127 or less than -128.

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Chapter # 8 Figure 8-8 Status register bits. 8-bit ALU F 7 – F 0 A B 8 8 C7C7 C8C8 Output F Check for zero output V ZSC F7F7 8

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Chapter # 8 Table 8-11 Conditional Branch Instructions MnemonicBranch conditionTested condition BZBranch if zeroZ = 1 BNZBranch if not zeroZ = 0 BCBranch if carryC = 1 BNC Branch if not carryC = 0 BPBranch if plusS = 1 BMBranch if minusS = 1 BVBranch if overflowV = 1 BNVBranch if not overflowV = 0 Unsigned compare conditions (A - B) BHIBranch if higherA > B BHEBranch if higher or equalA ≥ B BLOBranch if lowerA < B BLOEBranch if lower or equalA ≤ B (continue)

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Chapter # 8 Table 8-11 Conditional Branch Instructions (continued) MnemonicBranch conditionTested condition BEBranch if equalA = B BNEBranch if not equalA ≠ B Signed compare conditions (A - B) BGTBranch if greater than A > B BGEBranch if greater or equalA ≥ B BLTBranch if less than A < B BLE Branch if less or equal A ≤ B BEBranch if equalA = B BNEBranch if not equalA ≠ B

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Chapter # 8 Subroutine Call and Micro operations SP Sp – 1 Decrement stack pointer M[SP] PC Push content of PC onto stack PC effective address Transfer control to the subroutine Instruction from last subroutine is implement by following micro operations PC M[SP] Pop stack and transfer to PC SP SP + 1 Increment stack pointer

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Chapter # 8 State of CPU at the end of EXEC. Cycle (when the interrupt is recognized) is determined from. 1.The content of the program counter. 2.The content of all processor registers. 3.The content of certain status conditions.

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Chapter # 8 Types of Interrupts 1.External interrupts. 2.Internal interrupts. 3.Software interrupts.

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Chapter # 8 Major characteristics of CISC architecture. 1.A large number of instructions-typically from100 to 250 instructions. 2.Some instructions that performs specialized tasks and are used infrequently. 3.A large variety of addressing mode-typically from 5 to 20 different modes. 4.Variable-length instruction formats. 5.Instructions that manipulate operands in memory

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Chapter # 8 Major Characteristics of RISC architecture. 1.Relatively few instructions. 2.Relatively few addressing modes. 3.Memory access limited to load and store instructions. 4.All operations done within the registers of the CPU. 5.Fixed-length, easily decoded instruction format. 6.Single-cycle instruction execution. 7.Hardwired rather than micro programmed control.

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Chapter # 8 Figure 8-9 Overlapped register windows. R15 R10 R73 R54 R63 R58 R57 R48 R47 R42 R41 R32 R31 R26 R25 R16 R15 R10 R9 R0 Common to D and A Local to D Proc D Common to C and D Local to B Common to B and C Proc C Local to C Common to A and B Local to A Common to A and D Proc B Proc A Common to all procedures Global Registers

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Chapter # 8 Figure 8-10 Berkeley RISC I instruction formats. opcodeRdRs 0Not usedS (a) Register mode: (S2 specifies a register) opcodeRdRs 1S (a) Register-immediate mode: (S2 specifies a register) opcodeCOND Y (a) PC relative mode

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