1. CompE 460 Real-Time and Embedded Systems Lecture 5 – Hardware Fundamentals

2. Click to edit Master title style Agenda Prayer/Thoughts Team Presentation - Brandon Some Hardware Fundamentals Open Collector outputs Tri-state outputs Signal Overloading Circuit Timing Parameters Buses Address Maps Attaching multiple things on a bus –Wait states –Wait Signals –No Handshake PAL’s/FPGA’s Watchdog Timer

3. Click to edit Master title style Team Presentation Schematics

4. Click to edit Master title style Future Memory Technologies DVRAM (Deja-Vue RAM) the CPU thinks it has the data before it actually does PVRAM (Presque-Vue RAM) the CPU only has to pretend to access RAM to get the data ODRAM (Oracle at Delphi RAM) returns data the CPU plans to access next (first data access has to be a NOP). HRAM (Hearsay RAM) CPU talks to other CPUs and uses what they all think the data is, instead of accessing the data (which may be different) 711RAM (Seven-Eleven RAM) always available, but may be held up during the night shift ARAM (Audio RAM) like video RAM, but describes the image verbally instead MRAM (Mumble RAM) gumb dortle vrmrgish tord summblum sart groff tuldard snangle gnig

5. Click to edit Master title style What wrong with this? C DG A B F E

6. Click to edit Master title style PC Systems What is an interrupt (in computer terms)? On PC Systems, what are some sources of interrupts? USB Keyboard Disk Drive Mouse Network Card Graphics Card etc Now, a big dilemma. On many processors, there is only one low asserted interrupt pin. How can we hook up multiple interrupts to this one pin? C DG A B F E

7. Click to edit Master title style Multiple Interrupts on Same Line Open Collector Outputs - Standard parts drive signals either high or low. Some devices (called open collector devices) drive their signals low or let them float. uprocIC 2 IC 1 Vcc INT’ Why do we need the pull-up resistor?

8. Click to edit Master title style Data Bus With this configuration, what will happen if the SRAM tries to send data to the uproc at the same time as the Flash? Flash SRAM uproc Data Bus [d31:d0] How can we fix this?

9. Click to edit Master title style Tri-State Outputs Standard parts drive signals either high or low. Open collector devices drive their signals low or let them float. Tri-State devices can drive output high, low, or let them float. Used when you want more than one device to drive an input The outputs are enabled when the CS lines are true Sometimes need pullup/down resistor on tristate lines – Why? Figure 2.16 in text

10. Click to edit Master title style Data Bus CS (or sometime called OE lines) will allow only 1 device to drive the bus at a time. Flash SRAM uproc Data Bus [d31:d0] CS1 CS0

11. Click to edit Master title style Buses Simple processor example Microprocessor – A0 to A15, D0 to D7 ROM – 32k (15 address lines), 8 bit data RAM – 32k (15 address lines), 8 bit data

12. Click to edit Master title style Block Diagram What would the memory map look like for this?

13. Click to edit Master title style Memory Map ROM 0x00 to 0x7fff RAM 0x8000 to 0xffff 0x0000 0x7FFF 0x8000 0xFFFF ROM RAM

14. Click to edit Master title style How about other devices??? What about attaching keyboards, LCD’s, network chips, etc. How can we attach these types of devices to the microprocessor? What types of IO are available? Memory Mapped IO Isolated I/O space

15. Click to edit Master title style Isolated IO Space has separate spaces for IO and memory Isolated IO

16. Click to edit Master title style Memory Mapped IO uses the same space for IO and memory Memory Mapped IO

17. Click to edit Master title style PLD/FPGA … UProcRAMFlashUART Data, Address, Cntrl FPGA or CPLD A13 A14 A15 Clk RAMCE FlashCE UARTCE

18. Click to edit Master title style Signal Overloading What is signal overloading? Caused by connecting too many input circuits to a single output Also called Fan-out or loading problem How can you tell if you have a loading problem? Data Sheets specify the current a device is able to drive on its output lines Data Sheets also specify the current a device will typically source on its input lines How can you solve this? Figure 2.19 in text

19. Click to edit Master title style There is no such thing as Digital!!! All signals are really analog It takes a finite amount of time for a signal to travel from one point to another. High speed digital designers need to understand this Timing diagrams show actual AC timings including propagation delay. http://emp.byui.edu/FISHERR/All_Classes/Digital/74ls00.pdf

20. Click to edit Master title style Digital Circuit Timing There is a finite amount of time it takes for digital circuits to actually change state Ex. 74LS04 Propagation Delay is 15ns (max) A A’ A Something to think about - 800 MHz front side bus has clock period of 1.25 ns - 7404 Inverter gate has propagation delay of 15ns

21. Click to edit Master title style Digital Circuit Timing There are several key timing characteristics associated with digital circuits Propagation Delay Setup Time Hold Time Max Clock Frequency Clock pulse high and low times

22. Click to edit Master title style Propagation Delay Propagation Delay is the time it takes for the output of the circuit to change after the input has changed. Depending on technologies (TTL, CMOS, ECL, etc), propagation delay’s of modern IC’s range from <1ns to ~100ns.

23. Click to edit Master title style Setup Time The setup time is the time interval immediately preceding the active transition of the CLK signal during which the control input must be maintained at the proper level. If this time is not met, the FF may not respond to the CLK appropriately

24. Click to edit Master title style Hold Time Hold Time is the time interval immediately following the active transition of the CLK signal during which the synchronous control input must be maintained at the proper level. If this time is not met, the FF may not respond to the CLK appropriately

25. Click to edit Master title style Clock Frequency Spec’s Max Frequency (Fmax) - This is the highest frequency that may be applied to the CLK input and still have it trigger reliability Clock Pulse High (Twh) and Clock Pulse Low (Twl) Times – These are the minimum time duration that the clock signal must remain low before it goes high (Twl) and high before it returns low (Twh)

26. Click to edit Master title style Timings How can we ensure each device can talk to the microprocessor? 3 Methods Wait states – figure 3.6 and 3.7 Wait signal – figure 3.5 Buy fast enough parts - $$$

27. Click to edit Master title style Timings Typical Bus Read Cycle A0-An RD’ D0-Dn Clock uP drives Address bus to start bus cycle uP drives RD low Memory drives data bus uP reads data from bus End of bus cycle T1T2T3

28. Click to edit Master title style Timings 2-Wait State Bus Cycle A0-An RD’ D0-Dn Clock uP drives Address bus to start bus cycle uP drives RD low Memory drives data bus uP reads data from bus End of bus cycle T1T2T3 Tw

29. Click to edit Master title style Timings Wait Signal Bus Cycle A0-An RD’ D0-Dn Clock The slow device can assert WAIT as long as it needs, and the uP will wait T1T2T3 WAIT

30. Backup

31. Click to edit Master title style Watchdog Timer CPU Watch Dog Data, Address Bus and Cntrl Reset RST Glue logic Restart What kind of glue logic is this?

32. Click to edit Master title style DMA’s Direct Memory Access (DMA) Circuitry that can read/write data to/from an IO device and memory Independent from processor Need to have arbitration between DMA and processor

33. Click to edit Master title style DMA RAM IO CPU DMA Address Bus (rd/ wr/) Data Bus DMAREQ Bus ACKBus REQ

34. Click to edit Master title style DMA Timing A0-An D0-Dn Read DMA Request Bus Request Bus Ack Write IO Device drives the data bus DMA drives the data bus DMA drives IO device address on the bus DMA drives memory device address on the bus