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An Introduction to VHDL Using Altera’s Quartus II IDE Dr. William M. Jones Coastal Carolina University Numbers and Bytes Meeting 20 OCT 2008.

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Presentation on theme: "An Introduction to VHDL Using Altera’s Quartus II IDE Dr. William M. Jones Coastal Carolina University Numbers and Bytes Meeting 20 OCT 2008."— Presentation transcript:

1 An Introduction to VHDL Using Altera’s Quartus II IDE Dr. William M. Jones Coastal Carolina University Numbers and Bytes Meeting 20 OCT 2008

2 © 2007, William M. Jones, et. al.VHDL Quick Start2 Pre-Intro VHDL –Very Hard Difficult Language –Jk –VHSIC Hardware Description Language VHSIC –Very High Speed Integrated Circuits Intended uses –Circuit simulation –Circuit synthesis (realization) FPGA’s, (C)PLDs, ASICs

3 © 2007, William M. Jones, et. al.VHDL Quick Start3 Some Background VHDL vice Verilog Altera and Xilinx VHDL is a language –But, is very different from traditional languages –In general, all statements are CONCURRENT (parallel) –Traditional is SEQUENTIAL –Typically referred to as code as opposed to a program –VHDL is not case sensitive PROCESS, FUNCTION, PROCEDURE –Only places were sequential behavior is seen

4 © 2007, William M. Jones, et. al.VHDL Quick Start4 Basic VHDL Code Parts LIBRARY –Like #include in C or import in JAVA –Commonly used pieces of code –2 are generally included by default ENTITY –List of specifications for input and output PORTS –Kinda like function prototypes in C (provides interface) ARCHITECTURE –Provides a description of how the circuit should behave

5 © 2007, William M. Jones, et. al.VHDL Quick Start5 LIBRARY LIBRARY library_name; USE library_name.package_name.package_parts; LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY std; -- included by default USE std.standard.all; LIBRARY work; -- included by default USE work.all;

6 © 2007, William M. Jones, et. al.VHDL Quick Start6 ENTITY (Modeling Interfaces) (VHDL-93) Entity declaration –describes the input/output ports of a module entity reg4 is port ( d0, d1, d2, d3, en, clk : in bit; q0, q1, q2, q3 : out bit ); end entity reg4; entity nameport namesport mode (direction) port typereserved words punctuation

7 © 2007, William M. Jones, et. al.VHDL Quick Start7 PORTS – Signal Modes IN –Unidirectional OUT –Unidirectional INOUT –Bidirectional BUFFER –Used when output signal needs to be used internally

8 © 2007, William M. Jones, et. al.VHDL Quick Start8 Putting Them Together

9 © 2007, William M. Jones, et. al.VHDL Quick Start9 A Simple Multiplexer

10 © 2007, William M. Jones, et. al.VHDL Quick Start10 MUX Implementation with Pure Logic

11 © 2007, William M. Jones, et. al.VHDL Quick Start11 Synthesized Hardware (Pure Logic) But what do you do now?

12 © 2007, William M. Jones, et. al.VHDL Quick Start12 Altera DE 2 Board

13 © 2007, William M. Jones, et. al.VHDL Quick Start13

14 © 2007, William M. Jones, et. al.VHDL Quick Start14

15 © 2007, William M. Jones, et. al.VHDL Quick Start15

16 © 2007, William M. Jones, et. al.VHDL Quick Start16

17 © 2007, William M. Jones, et. al.VHDL Quick Start17

18 © 2007, William M. Jones, et. al.VHDL Quick Start18

19 © 2007, William M. Jones, et. al.VHDL Quick Start19 MUX Implementation with WHEN/ELSE

20 © 2007, William M. Jones, et. al.VHDL Quick Start20 Synthesized Hardware (WHEN/ELSE)

21 © 2007, William M. Jones, et. al.VHDL Quick Start21 A Simple ALU

22 © 2007, William M. Jones, et. al.VHDL Quick Start22 ALU Specifications

23 © 2007, William M. Jones, et. al.VHDL Quick Start23 ALU Part 1

24 © 2007, William M. Jones, et. al.VHDL Quick Start24 ALU Part 2

25 © 2007, William M. Jones, et. al.VHDL Quick Start25 ALU Part 3

26 © 2007, William M. Jones, et. al.VHDL Quick Start26

27 © 2007, William M. Jones, et. al.VHDL Quick Start27

28 © 2007, William M. Jones, et. al.VHDL Quick Start28

29 © 2007, William M. Jones, et. al.VHDL Quick Start29 Kickin’ It Up A Notch Combinational v. Sequential LOGIC

30 © 2007, William M. Jones, et. al.VHDL Quick Start30 Concurrent v. Sequential Code Code placed inside a PROCESS, FUNCTION, or PROCEDURE is executed sequentially Otherwise the does is executed concurrently –In parallel –Order of statements would not matter –Often called ‘dataflow’ code With only a few exceptions purely concurrent code will only produce ‘combinational’ circuits Sequential code must be employed to produce sequential logic circuits (this code can produce both in fact)

31 © 2007, William M. Jones, et. al.VHDL Quick Start31 A Simple Counter (Sequential Code Intro)

32 © 2007, William M. Jones, et. al.VHDL Quick Start32 Simple Counter Code

33 © 2007, William M. Jones, et. al.VHDL Quick Start33 Synthesized Hardware (Counter)

34 © 2007, William M. Jones, et. al.VHDL Quick Start34 Counter (Zoom 1)

35 © 2007, William M. Jones, et. al.VHDL Quick Start35 Counter (Zoom 2)

36 © 2007, William M. Jones, et. al.VHDL Quick Start36 A Counter With A Display

37 © 2007, William M. Jones, et. al.VHDL Quick Start37 Counter With Display VHDL (Part 1)

38 © 2007, William M. Jones, et. al.VHDL Quick Start38 Counter With Display (Part 2)

39 © 2007, William M. Jones, et. al.VHDL Quick Start39 Counter With Display (Part 3)

40 © 2007, William M. Jones, et. al.VHDL Quick Start40 Counter With Display (Part 4)

41 © 2007, William M. Jones, et. al.VHDL Quick Start41 Synthesized HW (Partial)

42 © 2007, William M. Jones, et. al.VHDL Quick Start42 Creating A Symbol File (Schematic)

43 © 2007, William M. Jones, et. al.VHDL Quick Start43

44 End of N&B Presentation Have a nice day!

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