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Introduction to Programmable Logic Devices and FPGAs Edward Freeman STFC Technology Department Detector & Electronics Division.

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1 Introduction to Programmable Logic Devices and FPGAs Edward Freeman STFC Technology Department Detector & Electronics Division

2 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) edward.freeman@stfc.ac.uk Lecture Outline n Introduction u Why Programmable Logic Devices and FPGAs n FPGA Field Programmable Gate Array u Architecture n Design Flow u Hardware Description Languages u Design Tools

3 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) edward.freeman@stfc.ac.uk Programmable Logic is a Key Underlying Technology for PP Experiments. n First-Level and High-Level Triggering n Data Transport (Networks) n Computers interacting with Hardware (Networks) n Silicon Trackers (Millions of Data Channels) Commercial Devices. Developments driven by Industry. Telecomms, Gaming, Aerospace, Automotive, Set-top boxes…. Why Programmable Logic Devices and FPGAs

4 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) edward.freeman@stfc.ac.uk CMS DAQ/Trigger Architectures CMS “Telecoms Network” ~ 1 Tbps Fully custom PP ASICs CPUs Commodity PCs Programmable Logic DIGITAL

5 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) edward.freeman@stfc.ac.uk Particle Physics Electronics n Special Dedicated Logic Functions (not possible in CPUs) u Ultra Fast Trigger Systems (Trigger Algorithms) Clock Accurate Timing u Massively Parallel Data Processing (Silicon Trackers with Millions of Channels) Custom Designed Printed Circuit Boards PCBs. Commercial Programmable Logic Devices, FPGAs

6 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) edward.freeman@stfc.ac.uk Lecture Outline n Introduction u Why Programmable Logic Devices and FPGAs n FPGA Field Programmable Gate Array u Architecture n Design Flow u Hardware Description Languages u Design Tools

7 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) edward.freeman@stfc.ac.uk Digital Logic Logic Gates Transistor Switches < 40 nm ! $$$ MOORE’S LAW

8 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) edward.freeman@stfc.ac.uk Digital Logic Black Box SUM of PRODUCTS Truth Table (Look Up Table LUT) Digital Logic Function 3 Inputs Product AND (&) Sum OR (|)

9 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) edward.freeman@stfc.ac.uk Digital Logic Black Box SUM of PRODUCTS Truth Table (Look Up Table LUT) Digital Logic Function 3 Inputs Product AND (&) Sum OR (|)

10 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) edward.freeman@stfc.ac.uk Logic Blocks n Logic Functions implemented in Look Up Table LUTs. n Flip-Flops. Registers. Clocked Storage elements. n Multiplexers (select 1 of N inputs) FPGA Fabric Logic Block

11 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) edward.freeman@stfc.ac.uk Look Up Tables LUTs n LUT contains Memory Cells to implement small logic functions n Each cell holds ‘0’ or ‘1’. n Programmed with outputs of Truth Table n Inputs select content of one of the cells as output n Configured by re-programmable SRAM memory cells 3 Inputs LUT -> 8 Memory Cells Static Random Access Memory SRAM cells 3 – 6 Inputs Multiplexer MUX

12 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) edward.freeman@stfc.ac.uk Logic Blocks n Larger Logic Functions built up by connecting many Logic Blocks together

13 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) edward.freeman@stfc.ac.uk Logic Blocks n Larger Logic Functions built up by connecting many Logic Blocks together n Determined by SRAM cells SRAM cells

14 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) edward.freeman@stfc.ac.uk Sequential Circuits Register CLOCK New Output every clock edge Shift Registers, Pipelines, Finite State Machines … n Combinational Logic (Larger circuits difficult to predict) n Synchronous Logic driven by a CLOCK n Registers, Flip Flops (Memory) Clock Rate determines speed Comb Logic Must meet Timing => Predictable circuits Inputs Intermediate EDGES

15 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) edward.freeman@stfc.ac.uk Clocked Logic n Registers on outputs. CLOCKED storage elements. n Synchronous FPGA Logic Design, Pipelined Logic. n FPGA Fabric Pulse from Global Clock (e.g. LHC BX frequency) FPGA Fabric Clock from Outside world (eg LHC bunch frequency) Special Routing for Clocks

16 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) edward.freeman@stfc.ac.uk Field Programmable Gate Arrays FPGA n Field Programmable Gate Array u ‘Simple’ Programmable Logic Blocks u Massive Fabric of Programmable Interconnects u Standard CMOS Integrated Circuit fabrication process as for SRAM memory chips (Moore’s Law) u “Hard blocks” for complex high speed functions Huge Density of Logic Block ‘Islands’ 1,000 … 100,000’s in a ‘Sea’ of Interconnects FPGA Architecture

17 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) edward.freeman@stfc.ac.uk Field Programmable Gate Arrays FPGA

18 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) edward.freeman@stfc.ac.uk Input Output I/O Getting data in and out Up to > 1,000 I/O “pins” (several 100 MHz) Special I/O SERIALISERS ~ 10 Gbps transfer rates Optical TRx

19 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) edward.freeman@stfc.ac.uk Lecture Outline n Introduction u Why Programmable Logic Devices and FPGAs n FPGA Field Programmable Gate Array u Architecture n Design Flow u Hardware Description Languages u Design Tools

20 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) edward.freeman@stfc.ac.uk Designing Logic with FPGAs n Design Capture. n High level Description of Logic Design. u Graphical descriptions u Hardware Description Language (Textual)

21 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) edward.freeman@stfc.ac.uk Hardware Description Languages n Language describing hardware (Engineers call it FIRMWARE) n Doesn’t behave like “normal” programming language ‘C/C++’ n Describe Logic as collection of Processes operating in Parallel n Language Constructs for Synchronous Logic n Compiler (Synthesis) Tools recognise certain code constructs and generates appropriate logic n Not all constructs can be implemented in FPGA! n 2 Popular languages are VHDL, VERILOG n Easy to start learning… Hard to master!

22 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) edward.freeman@stfc.ac.uk VHDL ENTITY Declaration Input Output to Module (STD LOGIC) SIGNALS Declaration WIRES CONCURRENT ASSIGNMENTS CONDITIONAL ASSIGNMENTS => MULTIPLEXERS

23 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) edward.freeman@stfc.ac.uk VHDL COMPONENT Declaration PROCESS Declaration. CONCURRENT functions. Synchronous Logic.

24 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) edward.freeman@stfc.ac.uk Designing Logic with FPGAs n High level Description of Logic Design u Hardware Description Language (Textual) n Compile (Synthesis) into NETLIST. n Boolean Logic Gates. n Target FPGA Device u Mapping u Routing n Bit File for FPGA n Commercial CAE Tools (Complex & Expensive) n Logic Simulation Design Flow

25 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) edward.freeman@stfc.ac.uk Configuring an FPGA n Millions of SRAM cells holding LUTs and Interconnect Routing n Volatile Memory. Lose configuration when board power is turned off. n Keep Bit Pattern describing the SRAM cells in non-Volatile Memory e.g. PROM or Digital Camera card n Configuration takes ~ secs JTAG Testing JTAG Port Programming Bit File

26 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Not just logic n Hard blocks (built into the FPGA) u High speed serialises (1Gb, 10Gb, hyper-transport ect) u Complex multiplier units (DSP) u Embedded processors (PPC404, PPC440, ARM Cortex-A9) u PCI express (Gen 2) u Multi clock multi phase clock managers. u Built in ultra fast RAMs u Programmable IO. (LVDS, SSTL and 100’s of others) n Plus the millions of gates of programmable logic from the FPGA fabric its self. edward.freeman@stfc.ac.uk

27 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Serialisers n A number of types and speeds. u We are currently supporting projects with multi 1Gb Ethernet readout. u 10Gb is working in the lab and 1 st boards are in testing now u PCI express endpoint (Gen 1) u Camera link edward.freeman@stfc.ac.uk PCI express Can use off the self switches to make backend system

28 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Embedded processors and multipliers n Processors u Fast image processing and control loop feedback in C code software. (20KHz image rate) u Large ping pong (image) frame buffer u System monitoring, house keeping, reporting and logging u Can also have an army of small “soft” processor cores n Multipliers (DSP blocks) u Complex FFT for machine frequency control. edward.freeman@stfc.ac.uk

29 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Block RAMs and Clock managers n Block RAMs u Small high speed buffers u Look up tables and scratch pads. u FIFO’s to help adjust data rates between processing blocks. n Clock Managers u Generate different frequency's from a reference clock. u Generate phase shits of the clocks. u Distribute the clocks to the different areas of the FPGAs (Not of much interest but nothing works without them) edward.freeman@stfc.ac.uk

30 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Other technology you can add to an FPGA n Memory interfaces u DRAM, DDR, QDR, SRAM, ZBTRAM ect. u Industry standard memory modules DDR2, DDR3, n Maths functions u Floating point units u Complex Multiplier u Integer Add, Sub, Multiply, Div u Digital signal processing functions FFT, FIR, reed-solomon encoders n Or any other digital system that can be described with custom logic. edward.freeman@stfc.ac.uk

31 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) edward.freeman@stfc.ac.uk Field Programmable Gate Arrays FPGA n Large Complex Functions n Re-Programmability, Flexibility. n Massively Parallel Architecture n Processing many channels simultaneously cf MicroProcessor n Fast Turnaround Designs n Standard IC Manufacturing Processes. Moore’s Law n Mass produced. Inexpensive. n Many variants. Sizes. Features. n PP Not Radiation Hard  n Power Hungry  n No Analogue 

32 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) edward.freeman@stfc.ac.uk FPGA Trends n State of Art is 32nm on 300 mm wafers n Top of range >500,000 Logic Blocks n >1,000 pins (Fine Pitched BGA) n Logic Block cost ~ 1$ in 1990 n Today < 0.1 cent n Problems u Power. Leakage currents. u Design Gap F CAE Tools ?

33 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) edward.freeman@stfc.ac.uk Summary n FPGA Field Programmable Gate Arrays u Architecture n Design Flow u Hardware Description Languages u Design Tools u Exploit industry hardware and protocols Importance for Particle Physics Experiments

34 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) edward.freeman@stfc.ac.uk References and contacts n The Design Warrior’s Guide to FPGAs u Clive Maxfield, Newnes Elsevier n FPGA manufacturer web sites u www.xilinx.com www.xilinx.com u www.altera.com www.altera.com n FPGA Online u www.pldesignline.com www.pldesignline.com u www.fpgajournal.com www.fpgajournal.com u www.doulos.com www.doulos.com n Technology u Rob Halsall – Rob.Halsall@stfc.ac.ukRob.Halsall@stfc.ac.uk u John Coughlan – John.Coughlan@stfc.ac.ukJohn.Coughlan@stfc.ac.uk

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