1. Registers & Counters M. Önder Efe onderefe@cs.hacettepe.edu.tr

2. Registers Registers are clocked sequential circuits A register is a group of flip-flops – Each flip-flop capable of storing one bit of information – An n-bit register consists of n flip-flops capable of storing n bits of information – besides flip-flops, a register usually contains combinational logic to perform some simple tasks – In summary flip-flops to hold information combinational logic to control the state transition

3. Counters A counter is essentially a register that goes through a predetermined sequence of states “Counting sequence” RegisterFF 0 FF 1 FF n-1 Combinational logic

4. Uses of Registers and Counters Registers are useful for storing and manipulating information – internal registers in microprocessors to manipulate data Counters are extensively used in control logic – PC (program counter) in microprocessors

5. 4-bit Register (Parallel) REG Q3Q3 Q2Q2 Q1Q1 Q0Q0 D3D3 D2D2 D1D1 D0D0 clear D Q clock C R D Q C R D Q C R D Q C R clear D0D0 D1D1 D2D2 D3D3 Q0Q0 Q1Q1 Q2Q2 Q3Q3

6. 4-bit Register (Parallel) module parallel_reg(Q3,Q2,Q1,Q0,D3,D2,D1,D0,clock,clear); output Q3,Q2,Q1,Q0; input D3,D2,D1,D0,clock,clear; reg Q3,Q2,Q1,Q0; always @(posedge clock or negedge clear) if(~clear) {Q3,Q2,Q1,Q0}<=4'b0000; else begin Q3 <= D3; Q2 <= D2; Q1 <= D1; Q0 <= D0; end endmodule

7. Register with Parallel Load Load D Q C R Q0Q0 D Q C R Q1Q1 D Q C R Q2Q2 D Q C R Q3Q3 clock clear D1D1 D2D2 D3D3 D0D0

8. 4-bit Parallel Register with Load module parallel_reg(Q3,Q2,Q1,Q0,D3,D2,D1,D0,clock,clear,Load); output Q3,Q2,Q1,Q0; input D3,D2,D1,D0,clock,clear,Load; reg Q3,Q2,Q1,Q0; always @(posedge clock or negedge clear) if(~clear) {Q3,Q2,Q1,Q0}<=4'b0000; else if(Load) begin Q3 <= D3; Q2 <= D2; Q1 <= D1; Q0 <= D0; end endmodule

9. Shift Registers A register capable of shifting its content in one or both directions – Flip-flops in cascade serial input serial output D Q C SI D Q C D Q C D Q C SO clock The current of n-bit shift register state can be transferred in n clock cycles

10. Shift Left Register module shift_reg(serial_output,serial_input,clock); output serial_output; input serial_input,clock; reg out3,out2,out1,out0; assign serial_output=out3; always @(posedge clock) begin out3 <= out2; out2 <= out1; out1 <= out0; out0 <= serial_input; end endmodule

11. Universal Shift Register Capabilities: 1.A “clear” control to set the register to 0. 2.A “clock” input 3.A “shift-right” control 4.A “shift-left” control 5.n input lines & a “parallel-load” control 6.n parallel output lines

12. Universal Shift Register Mode Control Register operation s1s1 s0s0 00No change 01Shift right 10Shift left 11Parallel load

13. 4-Bit Universal Shift Register D Q C D Q C D Q C D Q C A0A0 A1A1 A2A2 A3A3 parallel outputs clear clk 4  1 MUX 0 1 23 4  1 MUX 0 1 23 4  1 MUX 0 1 23 4  1 MUX 0 1 23 s1s1 s0s0 serial input for shift-right serial input for shift-left parallel inputs

14. Verilog Code – v1 // Behavioral description of a 4-bit universal shift register module Shift_Register_4_beh ( // V2001, 2005 output reg [3: 0] O_par, // Register output input [3: 0] I_par, // Parallel input input s1, s0, // Select inputs MSB_in, LSB_in, // Serial inputs CLK, // Clock Clear); // Clear always @ ( posedge CLK, negedge Clear) // V2001, 2005 if (Clear== 0) O_par <= 4'b0000; else case ({s1, s0}) 2'b00: O_par <= O_par; // No change 2'b01: O_par <= {MSB_in, O_par[3: 1]}; // Shift right 2'b10: O_par <= {O_par[2: 0], LSB_in}; // Shift left 2'b11: O_par <= I_par; // Parallel load of input endcase endmodule

15. Verilog Code – v2 // Behavioral description of a 4-bit universal shift register module Shift_Register_4_beh ( // V2001, 2005 output reg [3: 0] O_par, // Register output input [3: 0] I_par, // Parallel input input s1, s0, // Select inputs MSB_in, LSB_in, // Serial inputs CLK, // Clock Clear); // Clear always @ ( posedge CLK, negedge Clear) // V2001, 2005 if (Clear== 0) O_par <= 4'b0000; else case ({s1, s0}) // 2'b00: O_par <= O_par; // No change 2'b01: O_par <= {MSB_in, O_par[3: 1]}; // Shift right 2'b10: O_par <= {O_par[2: 0], LSB_in}; // Shift left 2'b11: O_par <= I_par; // Parallel load of input endcase endmodule

16. DQDQDQDQ IN OUT1OUT2OUT3OUT4 CLK OUT Pattern Recognizer Combinational function of input samples – In this case, recognizing the pattern 1001 on the single input signal

17. Counters Registers that go through a prescribed sequence of states upon the application of input pulses – input pulses are usually clock pulses Example: n-bit binary counter – count in binary from 0 to 2 n -1 Classification 1.Synchronous counters flip-flops receive the same common clock as the pulse 2.Ripple counters (Asynchronous) flip-flop output transition serves as the pulse to trigger other flip-flops

18. Binary Ripple Counter 00 0 0 10 0 1 20 1 0 30 1 1 41 0 0 51 0 1 61 1 0 71 1 1 00 0 0 3-bit binary ripple counter Idea: – to connect the output of one flip-flop to the C input of the next high-order flip- flop We need “complementing” flip-flops – We can use T flip-flops to obtain complementing flip-flops or – JK flip-flops with its inputs are tied together or – D flip-flops with complement output connected to the D input.

19. 4-bit Binary Ripple Counter T Q C R A0A0 T Q C R A1A1 T Q C R A2A2 T Q C R A3A3 clear count logic-1 D Q C R A0A0 D Q C R A1A1 D Q C R A2A2 D Q C R A3A3 clear count 00 0 10 0 0 1 20 0 1 0 30 0 1 1 40 1 0 0 50 1 60 1 1 0 70 1 1 1 81 0 0 0 91 0 0 1 10 111 0 1 1 121 1 0 0 131 1 0 1 141 1 1 0 151 1 00 0 Discouraged Know it exists Don’t use it

20. 4-bit Binary Ripple Counter T Q C R A0A0 T Q C R A1A1 T Q C R A2A2 T Q C R A3A3 clear count logic-1

21. 4-bit Binary Synchronous Counter Logic between registers (not just multiplexer) – XOR decides when bit should be toggled – Always for low-order bit, only when first bit is true for second bit, and so on

22. Binary Counter Verilog module binary_counter(out4, out3, out2, out1, clk); output out4, out3, out2, out1; input clk; reg out4, out3, out2, out1; always @(posedge clk) begin out4 <= (out1 & out2 & out3) ^ out4; out3 <= (out1 & out2) ^ out3; out2 <= out1 ^ out2; out1 <= out1 ^ 1b'1;//out1 <= ~out1; end endmodule

23. Binary Counter Verilog module binary_counter(out, clk); output [3:0] out; input clk; reg [3:0] out; always @(posedge clk) out <= out + 1; endmodule

24. Synchronous Counters There is a common clock – that triggers all flip-flops simultaneously – If T = 0 or J = K = 0 the flip-flop does not change state. – If T = 1 or J = K = 1 the flip-flop does change state. Design procedure is so simple – no need for going through sequential logic design process – A 0 is always complemented – A 1 is complemented when A 0 = 1 – A 2 is complemented when A 0 = 1 and A 1 = 1 – so on 00 0 0 10 0 1 20 1 0 30 1 1 41 0 0 51 0 1 61 1 0 71 1 1 00 0 0

25. 4-bit Binary Synchronous Counter J Q C A0A0 J Q C A1A1 J Q C A2A2 J Q C A3A3 K K K K clock Count_enable to next stage

26. Other Counters Ring Counter – A ring counter is a circular shift register with only one flip-flop being set at any particular time, all others are cleared. shift right Q3Q3 Q2Q2 Q1Q1 QoQo initial value 1000 Usage –Timing signals control the sequence of operations in a digital system In this case, 1000, 0100, 0010, 0001 If one of the patterns is its initial state (by loading or set/reset)

27. Ring Counter Sequence of timing signals clock Q3Q3 Q2Q2 Q1Q1 Q0Q0

28. Ring Counter To generate 2 n timing signals, – we need a shift register with ? flip-flops or, we can construct the ring counter with a binary counter and a decoder 2x4 decoder Q3Q3 Q2Q2 Q1Q1 Q0Q0 2-bit counter count Cost: 2 flip-flops 2-to-4 line decoder Cost in general case: n flip-flops n-to-2 n line decoder 2 n n-input AND gates n NOT gates

29. Ring Counter Verilog module ring_counter(Q,Clock,Resetn); input Clock,Resetn; output [3:0] Q; reg [3:0] Q; always @(posedge Clock or negedge Resetn) if(!Resetn) Q <= 4'b1000; else Q <= {Q[0],Q[3:1]}; //Q[3]<=Q[0]; //Q[2]<=Q[3]; //Q[1]<=Q[2]; //Q[0]<=Q[1]; endmodule

30. Johnson Counter A k-bit ring counter can generate k distinguishable states The number of states can be doubled if the shift register is connected as a switch-tail ring counter clock D Q C D Q C D Q C D Q C X X’ Y Y’ Z Z’ T T’ In this case, 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001

31. Johnson Counter Verilog module johnson_counter(X,Y,Z,T,clock,Resetn); input clock,Resetn; output X,Y,Z,T; reg X,Y,Z,T; always @(posedge clock or negedge Resetn) if(!Resetn) {X,Y,Z,T} <= 4'b0000; else X <= ~T; Y <= X; Z <= Y; T <= Z; endmodule

32. Rising Edge Detector ("0" to "1" transition) Verilog Kodu?

33. Falling Edge Detector ("1" to "0" transition) Verilog Kodu?

34. Edge Detector (Rising or Falling Edge Detector) ("1" to "0" or "0" to "1" transition) ?