1. PSoC 3 / PSoC 5 102: System Resources

2. Section Objectives Objectives, you will be able to:
Understand the system block diagram of PSoC 3 / PSoC 5 devices
Understand and use the PSoC 3 / PSoC 5 System Resources, including:
Power system
Programming & debugging
Configuration and boot process
Resets
Clocking
Memory & mapping
DMA and PHUB
I/O
Interrupts 2

3. System Block Diagram

4. Power System and Supplies (no boost)
Standard Power Configuration
No boost pump
Vdda Vddd >= Vddio0/1/2/3
Vdda = 1.8 – 5.5V
Supply Rules & Usage
Vdda: Must be highest voltage in system. Supplies analog high voltage domain and core regulator.
Vddd: Supplies digital system core regulators
Vcca: Output of the analog core regulator. An external 1.3 uF capacitor to ground is required.
Vccd: Output of the digital core regulator. A single external 1.3 uF capacitor to ground is required. Both Vccd pins must be tied together on the PCB and share the single 1.3 uF capacitor.
Vddio0/1/2/3: Independent I/O supplies. May be any voltage in the range of 1.8V to Vdda
This diagram demonstrates the most common power supply setup in most systems. This example does not use the boost converter and the digital and analog supplies are tied together at greater. The analog and digital supplies are greater than 1.8V requiring the use of the internal core regulators.
Vdda must always be the highest supply in the system. Vdda supplies power to all the high voltage analog circuitry on the device. Vdda is separate from the digital supply in order to minimize noise on the sensitive analog circuitry. Vdda supplies power to the analog core 1.8V regulator.
Vddd supplies power to all the high voltage digital circuitry as well as the digital 1.8V core regulator.
Vcca supplies power to the 1.8V analog core circuitry. A 1.3uF capacitor is required for regulator stability.
Vccd supplies power to the 1.8V digital core circuitry. A single 1.3uF capacitor tied directly to both Vccd pins is required for regulator stability. The Vccd pin must be tied together external to the chip.
Vddio0-3 allow independent power supplies to each quadrant of the chip. Each Vddio may be any voltage between 1.71V and Vdda. Each Vddio can supply up to 100mA to the IO pins that it supplies. On 68-pin and 100-pin devices each set of IO associated with a Vddio can sink up to 100mA, 48-pin devices can sink up to 100mA for each two Vddio, details in pin section of datasheet.
0.1uF bypass caps are recommended immediately next to all supply pins.
Many other power supply connection scenarios are possible for specific application requirements.

5. Power System (with boost)
Boost Converter Configuration
Used to generate up to 5.0V (Vout)
Battery voltage as low as 0.5V (Vbat)
Output voltage and current limit based on input voltage and boost ratio
75 mA max current
0.5 – 0.8V Vbat provides max of 1.95V Vout
Schottky diode required when Vout is >3.6V
Synchronous rectification maximizes efficiency
Boost may be used to power external circuits independent of PSoC Vdda and Vddd voltage
If boost not used:
Vssb, Vbat and Vboost must be tied to ground
Ind left floating
Boost converter is able to boost any voltage down to 0.5V (can start at 0.5V) up to 5.0V. ).5V is important as this is the voltage output from a single solar panel cell.
Output current is proportional to the boost ratio and input voltage. Datasheet details the max current under all uses scenarios. 75mA is the max output
For Vbat input voltages between 0.5 and 0.8V the output voltage is limited to a maximum of 1.91 volts.
A Schottky diode is required when Vout is greater than 3.6V as the diode power dissipation exceeds the capabilities of the internal diode. Internally the boost converter provides synchronous rectification to increase efficiency. Efficiency is typically 90% but depends greatly on input and output voltages.
The boost converter does not need to be used to power the PSoC device as it is capable of supplying any system device within current limitations. An example is a system that runs at 3.3V and has a 3.3V supply but has a sensor that requires 5.0V to operate. The boost converter can be used to only supply the 5.0V sensor.
If the boost convert is not used in a design then all of the boost converter pins must be tied to ground except the inductor pin which must be left floating.
The most common components used are a 10uH inductor and a 22uF filter capacitor. More design guidance example will be provided in an application note being developed.

6. Programming & Debug Interfaces
January 11, 2002
Programming & Debug Interfaces
JTAG
Legacy 4-wire Interface
Supports all programming and debug features
Serial Wire Debug (SWD)*
Standard 2-wire interface for all CY tools and kits
Supports all programming and debug features with same performance of JTAG
Default debug interface in PSoC Creator
Serial Wire Viewer (SWV)
Supports 32 mailboxes for application “printf” type debug
Uses only 1 pin
SWD is default interface
SWD is the new ARM standard for programming and debug because it provides the same programming and debug performance and features of JTAG but only requires 2 pins vs 4 or 5.
JTAG is still useful in the following three situations.
Existing production or bulk programmers only support JTAG and are unable to be updated with SWD support
System level boundary scan is required as only the JTAG interface supports the PSoC3/5 boundary scan capability
Multiple JTAG devices are required to be chained together on one JTAG connector/interface as SWD does not support device chaining. 8

7. Programming and General Features
January 11, 2002
Programming and General Features
Standard Flash Operations
Erase all
Erase block – 256 blocks per device independent of Flash size
Program block
Set block security (4 levels same as PSoC 1):
Unprotected – No protection
Factory Upgrade – Prevents external read
Field Upgrade – Prevents external read and write
Full Protection – Prevents external read and write as well as internal write
General Features available through JTAG/SWD
IO boundary scan through JTAG interface
Enable/Disable JTAG and SWD interfaces
On Chip Debug features enabled/disabled by firmware
Note: Disable OCD to help prevent reverse engineering
The primary use of the JTAG and SWD interfaces is to provide programming of the PSoC3/5 devices.
Flash programming is very similar to PSoC1 devices, with erase and programming operations occurring on blocks of Flash. In PSoC1 devices the Flash was typically 64 bytes per block. In PSoC3/5 devices the number of blocks is fixed at 256 with the size of the block changing based on flash size. For example 64KB Flash devices have 256 blocks of 256 bytes each.
Each Flash block has 4 protection levels, they are the same as PSoC1.
JTAG and SWD interfaces also provide several general features useful at programming time.
IO boundary scan is available through the JTAG interface providing board level electrical testing
The JTAG and SWD interfaces may be independently enabled or disabled to maximize GPIO availability for the users application
On Chip Debug (OCD) is disabled by default and can not be enabled through the JTAG or SWD interfaces. OCD can only be enabled by a register write from within the users firmware.
PSoC3/5 devices provide a method to PERMANTLY disable the debug and programming capabilities of the device. The user may still use JTAG or SWD to check the system state to see that it has been permanently disabled but nothing else is available. This is very strongly not recommended for most designs as this makes the device One Time Programmable (OTP) and most FA analysis tests become impossible. Only physical device damage can be checked. The intended use case of this feature is for applications that require a level of phishing protection. This feature blocks a malicious user from replacing the firmware within the device with new firmware. 8

8. On Chip Debug (OCD) Debug Features: Trace Details
January 11, 2002
On Chip Debug (OCD)
Debug Features:
Trace Details
PSoC 3 – 4k on chip instruction trace included in all devices. Trace memory may be used as system memory
PSoC 5 – Select devices include ARM External 5-wire Trace Macrocell supporting ETM, ITM and DWT
1 PC Memory Dependant
Trace support in PSoC Creator coming in later release
PSoC3/5 devices provide On Chip Debug (OCD) on every devices through standard JTAG or SWD interfaces. No pods or In Circuit Emulators (ICE) are required. All customers can debug in system without mechanical Pod constraints.
Debug capabilities are very similar to PSoC1 devices with ICE cube with the following key differences.
The maximum number of breakpoints reduced to 8 for 8051 and 6 for ARM cores which is more than sufficient for most application debugging needs
Complex events are not supported in PSoC3/5 devices although some simple event capabilities are possible with chaining of the program and address breakpoints and trace buffer control.
PSoC1 provided 128k of trace memory in the ICE cube, PSoC3 devices provide 4k of trace memory on all devices. If the user does not need trace capability the 4k trace memory can be used for application memory instead. PSoC5 support the ARM standard TRACEPORT interface for ETM trace which streams compressed trace data directly to a PC with trace memory limits being software dependant. A second MiniProg3 is required to provide simultaneous Debug and Trace On PSoC5 devices.
Detailed training of ARM Cortex M3 trace features as well as trace support under development in PSoC creator will be provided at the PSoC5 launch training. 8

9. January 11, 2002
Reset Sources
PPOR - Power On Reset XRES - External reset pin PRES - Under voltage on external supplies Vddd, Vdda PRES - Under voltage on internal supplies Vccd, Vcca AHVI - Over voltage on Vdda HRES - Hibernate mode under voltage detect SRES - User software and/or hardware generated reset WRES - Watchdog reset JTAG or SWD interface generates reset 8

10. January 11, 2002
Clocking Sources
Internal Main Oscillator: 3-67 MHz. (±1% at 3 MHz; ±5% at 67 MHz) PLL output: MHz (can not use 32 kHz crystal) External clock crystal input: 4-33 MHz External clock oscillator inputs: 0-33 MHz Clock doubler output: MHz Internal Low speed oscillator: 1 kHz, 33 kHz and 100 kHz External 32 kHz crystal input for RTC
PLL 4 - 33
MHz
ECO 32
kHz 3 67
IMO
Ext Osc 1 ,
100
ILO
Table 6-1. Oscillator Summary (From CY8C38xxx datasheet):
IMO 3 MHz ±1% over voltage and temperature 67 MHz ±5% 10 μs max
MHzECO 4 MHz Crystal dependent 33 MHz Crystal dependent 5 ms typ, max is crystal dependent
DSI 0 MHz Input dependent 33 MHz Input dependent Input dependent
PLL 12 MHz Input dependent 67 MHz Input dependent 100 μs max
Doubler 12 MHz Input dependent 48 MHz Input dependent 1 μs max
ILO 1 kHz -30%, +65% 100 kHz -20%, +30% 1000 μs max
kHzECO 32 kHz Crystal dependent 32 kHz Crystal dependent 500 ms typ, max is crystal dependent
Key features of the clocking system include:
􀂄 Seven general purpose clock sources
􀂇 3 to 67 MHz IMO ±1% at 3 MHz
􀂇 4 to 33 MHz External Crystal Oscillator (MHzECO)
􀂇 DSI signal from an external IO pin or other logic
􀂇 12 to 67 MHz fractional Phase-Locked Loop (PLL) sourced
from IMO, MHzECO, or DSI
􀂇 Clock Doubler
􀂇 1 kHz, 33 kHz, 100 kHz ILO for Watch Dog Timer (WDT) and
Sleep Timer
􀂇 kHz External Crystal Oscillator (kHzECO) for Real
Time Clock (RTC)
􀂄 IMO has a USB mode that auto locks to the USB bus clock
requiring no external crystal for USB. (USB equipped parts only)
􀂄 Independently sourced clock in all clock dividers
􀂄 Eight 16-bit clock dividers for the digital system
􀂄 Four 16-bit clock dividers for the analog system
􀂄 Dedicated 16-bit divider for the CPU bus and CPU clock
􀂄 Automatic clock configuration in PSoC Creator 8

11. Clock Distribution Clock dividers 16-bit dividers
January 11, 2002
Clock Distribution
Clock dividers
16-bit dividers
8 clock source inputs
8 digital clock dividers
4 analog clock dividers
Provide skew control to reduce digital switching noise
1 CPU divider
UDBs can be used to create additional digital clocks 3 - 67
MHz 4 - 33
MHz - 33
MHz 32
kHz 1 , 33 ,
100
kHz
IMO
ECO
Ext Osc
ECO
ILO
PLL 7 7
Digital Clock Divider 16 -
bit
Digital Clock Divider
Bus /
CPU Divider 16 -
bit 16 -
bit
Digital Clock Divider 16 -
bit
Digital Clock Divider 16 -
bit
Digital Clock Divider
Analog Clock Divider
Skew 16 -
bit 16 -
bit
Digital Clock Divider
Analog Clock Divider
Skew 16 -
bit 16 -
bit
Digital Clock Divider
Analog Clock Divider
Skew 16 -
bit 16 -
bit
Digital Clock Divider
Analog Clock Divider
Skew 16 -
bit 16 -
bit 8

12. System Clock Setup

13. Clock Management
Clocks allocated to dividers in clock tree Clocks have software APIs to dynamically change frequency Note: Reuse existing clocks to preserve resources
The tool will determine the closest source and divider ratio to generate the user requested frequency as closely as possible.

14. 8051 Memory Map Internal Data space (IDATA)
256 Bytes of SRAM
Standard 8051 specific SFR registers
Access port data registers through SFRs
External Data space (XDATA/16MB)
Up to 8 KB of SRAM on lead devices
All PSoC peripheral and configuration registers
EEPROM
Flash
External memory Interface (EMIF)

15. ARM Cortex-M3 Memory Map
Single 4 GB address space
Registers from 8051 map into 0.5 GB peripheral region’s bit band region for efficient bit operations

16. External Memory Interface (EMIF)
EMIF Supports:
Sync SRAM
Async SRAM
Cellular RAM
NOR Flash
EMIF Usage:
PSoC 3 – Data only
PSoC 5 – Data and program
8- or 16-bit data bus
8-,16- or 24-bit address bus
Max throughput MHz depending on configuration details 16

17. Software Use of Registers
8051 and ARM Cortex-M3
Provide same functionality/address mapping to all PSoC 3 / PSoC 5 registers
Use Peripheral Hub (PHUB) bus
Macros hide MCU/compiler differences enabling PSoC 3 / PSoC 5 portability
cytypes.h
CY_GET_REG8(addr)
CY_SET_REG8(addr, value)
cydevice_trm.h
Contains device register #defines
8051 includes SFR registers allowing direct register access
Affects portability to PSoC 5 if used
PSoC3_8051.h
Contains SFR register #defines

18. Flash Flash Blocks: Specs:
256 Blocks in all devices – 64 KB flash has 256 byte block size
Each block may be set to 1 of 4 protection levels of increasing security
Unprotected – Allows internal and external reads and writes
Factory Upgrade – Prevents external read
Field Upgrade – Prevents external read and write
Full Protection – Prevents external read and write as well as internal write
Flash is erased and programmed in block units
Specs:
Code executes out of Flash
Flash-writes block CPU unless executing from cache (PSoC 5 only)
20 year minimum retention
10k minimum endurance
15 ms block erase + write time
Flash security not yet supported in PSoC Creator…will be added wwXX

19. Error Correcting Code (ECC)
ECC = Flash Memory Error Correction
Required for some high reliability designs (e.g. automotive and medical)
Detects and corrects 1 bit of error
Detects but does not correct 2 bits of error
Correction is automatic, interrupt and flag bit are set
1 byte of ECC data for each 8 bytes of Flash data (1 row)
64 KB device includes +8 KB of ECC memory for 72 KB total
8 KB is used for configuration data storage if ECC not used (default)
ECC memory is mapped into contiguous region in peripheral space
ECC memory may also hold user data
Code can not execute out of ECC memory

20. EEPROM 2 KB of EEPROM are provided Code can not execute out of EEPROM
EEPROM Specs:
EEPROM writes do not block CPU execution
20 year minimum retention
100k minimum endurance
2 ms single byte erase + write time
Supports single byte erase and writes
May erase or write up to 16 consecutive bytes (1 row) at the same time.
Note: Any combination and number of bytes in a 16 byte row may be erased or written at the same time as long as they are located in the same row.

21. Nonvolatile Latches (NV latches)
Single Flash bits used to hold critical configuration data
Required at power up before normal Flash can be read
Used the same as fuse bits except resettable
Uniquely capable of asynchronously outputting the bit state immediately on POR release
NV Latch Specs:
10 minimum endurance (Like fuse bits, not programmed often)
20 year minimum retention
Set as required by PSoC Creator (System tab of DWRM)
NV Latches are used for:
Each IO Port’s initial reset state (High-Z, pull-up, pull-down)
Optional XRES pin (P1[2]) enable
Configuration Speed (fast, slow)
Debug Port Selection (4-wire JTAG, 5-wire JTAG, SWD, None)
Error Correcting Code (ECC) enable
Digital clock phase delay (2.5 – 12.5 ns)
The 10 cycle endurance is acceptable given the use case for NV latches. They are only programmed with external programmers and not programmed in system. They control optional POR features that are rarely changed and are not reprogrammed every time the chip Flash memory is reprogrammed.

22. Bootloaders Single Bootloader Supports I2C UART USB Others as required
January 11, 2002
Bootloaders
Single Bootloader Supports
I2C
UART
USB
Others as required
Bootloader Integration
Bootloader platform allows easy customization
No bootloader programmed in parts at factory
PSoC Creator integrates bootloader support seamlessly; just another component
Bootloader Framework
Communication
Interface
Flash
Programming 8

23. Peripheral Hub (PHUB) Interconnect between: Two potential masters
CPU
DMA
All peripherals
Two potential masters
DMA controller
Arbitrates between CPU and DMA
Priority based on spoke
Supports simultaneous DMA and CPU access on separate spokes
CPU is not a bus hog
Reduces power consumption
Translates:
Byte-order
Data width differences

24. Direct Memory Access (DMA)
24 hardware channels
8 priority levels with minimum bandwidth guarantees
128 Transaction Descriptors (TD) tell channel what to do
2kB of dedicated SRAM holds all TD data
Multiple channels or TDs may be chained or nested
Configurable burst size
DMA between peripherals on same spoke limited to 1-byte burst length
Supports bandwidth up to Max Bus clock speed (67 Mhz PSoC3, 80 MHz PSoC5) at the narrowest spokes word width (8, 16 or 32-bit)
Bandwidth guarantees provide a minimum percentage of bus available bandwidth. Priority levels 0 and 1 can each use up 100% of the available bus bandwidth. Priority levels 2-7 share up to 100% of the available bus bandwidth. For example if a priority level 0 DMA uses 80% of the available bus bandwidth then a priority level 1 DMA can use up to the remaining 20% of bus bandwidth.

25. GPIO - I/O Digital Features
January 11, 2002
GPIO - I/O Digital Features
Independent supply rails
Each quadrant of device has separate Vddio supply (100 mA max sink or source)
GPIO Vddio must be <= Vdda
Logic level max current
8 mA sink
4 mA source
Pin max current
~25 mA sink
~25 mA source
Pin max current numbers are approximate. Final numbers will be provided based on pending device characterization. 8

26. GPIO - I/O Digital Features
January 11, 2002
GPIO - I/O Digital Features
8 Drive Modes
New Resistive Pull-up & Down mode replaces PSoC Designer/PSoC1 Strong slow mode 8

27. GPIO - Interrupts Each GPIO port has: Interrupt on: Status Register
Port Interrupt Control Unit (PICU)
Dedicated interrupt vector
Interrupt on:
Rising edge
Falling edge
Any edge
Status Register
Latches which pin triggered interrupt
Available for firmware read
Read clear
Interrupt on Any Edge: (different than PSoC1 change from last read)

28. GPIO - I/O Analog Features
January 11, 2002
GPIO - I/O Analog Features
All pins inputs and outputs
Supports two independent analog connections at each pin
Some pins have additional routing features:
Opamps
High Current DAC mode
CapSense Touch Sensing
LCD char/segment drive
Hardware controlled analog mux at pin 8

29. SIO (Special I/O) Features
January 11, 2002
SIO (Special I/O) Features
Same as GPIO with exceptions:
5.5V tolerant at all Vdda levels
Hot Swap
Overvoltage tolerance
Configurable drive and sense voltage levels
Basic DAC output
High Speed CMP input
Logic level max current
25 mA sink
4 mA source
Pin max current
~50 mA sink
~25 mA source
No Analog
No LCD char/segment drive
No CapSense touch sensing
Pin max current numbers are approximate. Final numbers will be provided based on pending device characterization. 8

30. I/O Registers Standard port registers Orthogonal pin registers
January 11, 2002
I/O Registers
Standard port registers
Multiple register writes to configure a single pin
Able to configure whole port with a couple of register writes
Separate Port Status (PS) and Data Register (DR) for read, modify, write of port pins
Orthogonal pin registers
Configure 1 pin in a single write
Standard and Orthogonal register operations can be mixed on same pin
Orthogonal port register
Configure all pins in a port to same state with a single write 8

31. Software Use of I/O Registers
PHUB Bus Register Macros:
cytypes.h - Contains register macro definitions
cydevice_trm.h - Contains device register definitions
Port = CY_GET_REG8(CYREG_PRT0_DR);
CY_SET_REG8(CYREG_PRT0_DR, 0x04);
Use of SFR registers for 8051 provides direct register access, limits portability
PSoC3_8051.h - Contains SFR register #defines
SFRPRT0DR |= 0x04;
8051 provides efficient bit operations on port SFR registers
sbit bLed1 = SFRPRT0DR ^ 3;
bLed1 = 1;
Pin Component provides APIs like any other component
Pin_1_Write();
Pin_1_Read();
Pin_1_ReadDataReg();
Pin_1_SetDriveMode();
Pin_1_Clearinterrupt();

32. Pin Management PSoC Creator, CyFitter can select pins automatically
Best to let fitter have maximum flexibility to optimize entire design
Lock pins when device pin out is finalized
Manual override in DWR file

33. Interrupts Interrupt Controller 8051 ARM Cortex-M3
32 interrupt vectors
Dynamically adjustable vector addresses
8 priority levels
Each vector supports one of three sources
Fixed function, DMA, DSI (UDB) route
8051
32 interrupt vectors vs. standard 8051 is five
ARM Cortex-M3
32 interrupts + 15 exceptions
Tail chaining
Tail Chaining allows the processor to transition from the currently executing ISR directly to another pending ISR without having to spend the normally required cycles to restore state back to main and then store state again to get back to the other pending interrupt.

34. Interrupt Component
GUI Configuration API isr_1_Start() – Configures and enables the interrupt. Typically the only API required to be called Advanced APIs isr_1_SetVector() – Dynamically change vector address isr_1_SetPriority() – Dynamically change vector priority isr_1_GetPriority() – Read current priority isr_1_Enable() – Enable interrupt vector isr_1_GetState() – Return current state of interrupt vector enable isr_1_Disable() – Disable interrupt vector isr_1_SetPending() – Force a pending interrupt isr_1_ClearPending() – Clear a pending interrupt

35. Review You should now be able to:
Understand the system block diagram of PSoC 3 / PSoC 5 devices
Understand and use the PSoC 3 / PSoC 5 System Resources, including:
Power system
Programming & debugging
Configuration and boot process
Resets
Clocking
Memory & mapping
DMA and PHUB
I/O
Interrupts 35

36. Lab1 102: My First PSoC 3 Analog Design36

37. Lab Objectives Objectives:
Acquire an analog signal from the on board accelerometer and it to display LEDS as a carpenter’s level.
More experience with the PSoC Creator Design Flow 37

38. Step 1: Open ‘Lab 102 – My First PSoC3 Analog Design.cywrk’38

39. Step 2: Open TopDesign.cysch39

40. Step 3: Place/Configure Analog Pin40

41. Step 3: Place/Configure Analog Pin

42. Step 3: Place/Configure Analog Pin

43. Step 3: Place/Configure Analog Pin

44. Step 4: Place/Configure ADC44

45. Step 5: Wire Components 45

46. Step 6: Configure PSoC I/O46

47. Step 7: Review Firmware 47

48. Step 8: Build Project 48

49. Step 9: Program/Debug 49

50. Step 10: Debug 50