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 Seattle Pacific University EE 1210 - Logic System DesignCADNumbers-1 Arithmetic and CAD Tools CAD tools work great with arithmetic functions Adding,subtracting,multiplying,

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Presentation on theme: " Seattle Pacific University EE 1210 - Logic System DesignCADNumbers-1 Arithmetic and CAD Tools CAD tools work great with arithmetic functions Adding,subtracting,multiplying,"— Presentation transcript:

1  Seattle Pacific University EE 1210 - Logic System DesignCADNumbers-1 Arithmetic and CAD Tools CAD tools work great with arithmetic functions Adding,subtracting,multiplying, etc. A few things to learn first How to work with multi-bit numbers in CAD tools and VHDL How to create custom components in CAD tools I.e. a 7-bit adder/subtractor How to include VHDL components in a larger schematic

2  Seattle Pacific University EE 1210 - Logic System DesignCADNumbers-2 Multi-bit Numbers - Busses In Quartus II Schematics Busses are collections of wires mybus[7..0] is an eight bit bus Composed of mybus[7] (MSB) through mybus[0] (LSB) Busses make it easier to draw circuit diagrams In VHDL Busses are defined as a type of STD_LOGIC X: STD_LOGIC_VECTOR (7 DOWNTO 0) Composed of X(7) through X(0)

3  Seattle Pacific University EE 1210 - Logic System DesignCADNumbers-3 Connecting by name in Schematics Nodes (wires) can be connected by name Reduces complexity of drawing Input names Can be used on any wires All wires of the same name are connected Intermediate node names Just name it – no need to define it Busses Can connect a single wire from a bus by name

4  Seattle Pacific University EE 1210 - Logic System DesignCADNumbers-4 Busses in Schematics Many components have bus inputs Adders, for example Busses use thick lines Drawing from a bus input automatically makes a bus May select thick line from the line style menu Connecting busses Just name them the same thing Making busses out of wires Type all of the components (MSB to LSB) separated by commas

5  Seattle Pacific University EE 1210 - Logic System DesignCADNumbers-5 Creating and Using Custom Schematic Symbols 1. Make your component. Inputs/Outputs are interface to higher level 2. File | Create/Update | Create Symbol File For Current File 3. Make a new schematic for your main file and use your new symbol!

6  Seattle Pacific University EE 1210 - Logic System DesignCADNumbers-6 Making and Using Custom VHDL Symbols 1. Make your component. Inputs/Outputs are interface to higher level 2. File | Create/Update | Create Symbol File For Current File 3. Make a new schematic for your main file and use your new symbol!

7  Seattle Pacific University EE 1210 - Logic System DesignCADNumbers-7 MegaFunctions Quartus II has many configurable megafunctions Adders, subtractors, muxes, etc. Use the MegaWizard Button on the insert symbol menu Answer all of the questions see next slide… Save the new part Insert it into your schematic

8  Seattle Pacific University EE 1210 - Logic System DesignCADNumbers-8 Using the MegaWizard 1. Choose “Create a new…” to make a new device 2a. Pick a megafunction to use: Arithmetic includes adders, subtractors, counters, multipliers, etc. Gates include multiple-bit variations of standard logic. 2b. Choose VHDL and give your part a name.

9  Seattle Pacific University EE 1210 - Logic System DesignCADNumbers-9 Using the MegaWizard 3. Pick options: Data bus width Modes Etc.

10  Seattle Pacific University EE 1210 - Logic System DesignCADNumbers-10 Using the MegaWizard 4. Decide if any inputs are constants (i.e. always adding 4)

11  Seattle Pacific University EE 1210 - Logic System DesignCADNumbers-11 Using the MegaWizard 5. Pick optional outputs: Adder has optional carryin, carryout, and overflow out.

12  Seattle Pacific University EE 1210 - Logic System DesignCADNumbers-12 Using the MegaWizard 6. Pipelining – advanced option to speed up the function. Don’t use for now.

13  Seattle Pacific University EE 1210 - Logic System DesignCADNumbers-13 Using the MegaWizard 7. Just click Finish…

14  Seattle Pacific University EE 1210 - Logic System DesignCADNumbers-14 Using the MegaWizard 8. Yes – add to your project so you can use it! 9. Now your new symbol is available for use in schematics!

15  Seattle Pacific University EE 1210 - Logic System DesignCADNumbers-15 Using Busses in VHDL LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY hextosevenseg IS PORT( N: INSTD_LOGIC_VECTOR(3 downto 0); a,b,c,d,e,f,g,dec: OUTSTD_LOGIC); END hextosevenseg; ARCHITECTURE logicfunc OF hextosevenseg IS BEGIN a <= NOT( (N(2) AND N(1) AND NOT N(3)) OR (N(1) AND NOT N(2) AND N(0)) ); b <= … END logicfunc; Must use the IEEE library to use STD_LOGIC Bus definition Using bus signals individually

16  Seattle Pacific University EE 1210 - Logic System DesignCADNumbers-16 Math in VHDL LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_signed.all; ENTITY addemup IS PORT( A,B: INSTD_LOGIC_VECTOR(15 downto 0); Sum: OUTSTD_LOGIC_VECTOR(15 downto 0)); END addemup; ARCHITECTURE logicfunc OF addemup IS BEGIN Sum <= A + B; END logicfunc; Must use the SIGNED library for math It’s this easy! We’re adding two 16-bit numbers and producing a 16-bit sum

17  Seattle Pacific University EE 1210 - Logic System DesignCADNumbers-17 Decisions in VHDL using IF/THEN/ELSE LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_signed.all; ENTITY addemup IS PORT( A,B: INSTD_LOGIC_VECTOR(15 downto 0); Sub : IN STD_LOGIC; Out: OUTSTD_LOGIC_VECTOR(15 downto 0)); END addemup; ARCHITECTURE logicfunc OF addemup IS BEGIN PROCESS(Sub,A,B) BEGIN IF (Sub = ‘0’)THEN Out <= A + B; ELSIF (Sub = ‘1’)THEN Out <= A – B; ELSE Out <= “0000000000000000”; END IF; END PROCESS; END logicfunc; Expand adder to adder/subtractor: Sub=‘1’  subtract, Sub=‘0’  Add PROCESS: Identify which inputs may cause output to change IF / ELSIF / ELSE / END IF; Decision-making statements Don’t forget to END IF and PROCESS Vector constants in double quotes Scalar constants in single quotes

18  Seattle Pacific University EE 1210 - Logic System DesignCADNumbers-18 Truth Tables in VHDL LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY simplefunction IS PORT( A: INSTD_LOGIC_VECTOR(1 downto 0); Z,Q: OUTSTD_LOGIC); END simplefunction; ARCHITECTURE logicfunc OF simplefunction IS BEGIN PROCESS(A) BEGIN CASE A IS WHEN “00” => z z z z z<=‘0’;q<=‘0’; END CASE; END PROCESS; END logicfunc; “Others” catches any unlisted cases. Use it even if you covered them all. Process block specifies input(s) to process A case for each row in truth table Vector constants in double quotes Scalar constants in single quotes

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