2. Marek Perkowski’s Productions present: Lectures on Logic Synthesis Some slides come from various sources, including Adam Postula, Mark Schulz and U.C. Berkeley

3. ECE 572 Advanced Logic Synthesis Dr Marek Perkowski mperkows@ee.pdx.edu http://www.ee.pdx.edu/~mperkows Introduction Grading What is this class about

4. Do not take notes You will get all slides

5. PSU sequence of classes u This is a complete sequence related to digital logic design automation. ECE 171ECE 271 Logic Synthesis Sequential Circuits Winter Design with VHDL/VerilogSpring Formal Verification and DesignSpring Testing and Design for Test Fall Fall Quantum Computing

6. Objective of Subject u Students will have the understanding and experience of CAD/EDA techniques in combinational circuit design. u Students will be aware of state-of-the-art techniques in the realization of digital designs - specifically the use of Rapid Prototyping Techniques. u Students will learn modern EDA (Electronic Design Automation) approaches and fundamentals of building tools

7. What in coming weeks? u Look to my WWW Page. u Review and Introduction. u Properties of functions (symmetry, unateness, etc). u Representations of Functions, Relations and State Machines. u Spectral approaches u Spectral approaches based on transforms and diagrams u Applications outside circuit design.

8. Required Background ECE 171ECE 271 u You require, and are assumed to know, the material presented to you in ECE 171 and ECE 271 or equivalent u This material covered basic Boolean algebra, truth tables, Karnaugh maps (K-maps), simple minimization techniques using Karnaugh maps, and some basic design skills in Boolean algebra. but not a must u Knowledge of programming in C, C++, Java, Basic, Lisp or similar language is useful but not a must. animated PowerPoint u Everybody will create animated PowerPoint presentations and his WWW Page with a new material and project descriptions.

9. Review. What this part of the course covers. u Combinational Circuit Design –Review of Karnaugh Maps –Minimization of combinational logic circuits using Karnaugh Maps –CAD Techniques of combinational logic circuit minimization –Binary Decision Diagrams

10. Review. What this part of the course covers(cont). u Combinational Circuit Design –Functional Decomposition –Graph Coloring and Set Covering Techniques –MSI building blocks: multiplexers, decoders, ROM’s and PLA’s –Arithmetic circuits –Introduction to data structures and optimization

11. What is covered in the course? u Advanced Logic and Tools design –Advanced Decision Diagrams, –Two level minimization theory, graph coloring, Boolean Equations, implicit methods –Functional Decomposition –Reed-Muller Logic and Linearly Independent Logic

12. Grading System u Homeworks = 45 % u Midterm 1 = 15 % u Midterm 2 = 15 % u Final Exam = 25 % –Final examination (3 Hours or take home) - Questions from all the course, but with emphasis on the second half of the course. –Midterm Examination (open book, in class) –Homeworks –Presentations of homeworks

13. Remember that all exams are: Remember that I emphasize in this class not only hard work but also….

14. TEXTBOOKS u Strongly Recommended –Gary Hachtel and Fabio Somenzi, Logic Synthesis and Verification Algorithms, Kluwer Academic Publishers, 1996. –Randy Katz, Contemporary Logic Design, Benjamin/Cummings, 1994 –Perkowski and Mishchenko, 1999-2000 u Useful –Capilano Computing, LogicWorks 3, 1995 (includes 3.5” diskette for Windows). This is a simulation program.

15. Other Information u There is a WWW Home page for this subject. u Most PowerPoint 4.0 slides you see here, plus a Postscript printable version with 6 slides per page will be available. u Lectures will be available within 24 hours after the lecture is given (mainly because I will be completing the lectures on Sunday nights and Monday mornings prior to the lecture). u All sorts of other info will be there as well. u Class announcements will appear in the “class schedule” pages of this class at the WWW page of Marek Perkowski. u Assignment: u Assignment: Find this page using Google Engine. Type +Perkowski +Marek and next go to “Classes that I teach”

16. Other Information u Send emails with questions. u I will post news for class students of this group. I presume that it is read within 2 or 3 working days. YOU ARE RESPONSIBLE FOR READING THE NEWS IN CLASS SCHEDULE LINK!

17. Any Other Administrative Details? u ! Now is the time to ask

18. Design Example: Hall Light Design

19. u Problem Specification: –You are to design a device which will control the hall lights. There are two switches, one at each end of the hallway, and a light in the middle of the hall. The light can be turned on or off from either switch. –Give the truth table of the controller for this system. –Specify the truth table in its simplest form (ie, use a simplification or minimization technique).

20. Solution Step 1: Block Diagram u This is a BLOCK DIAGRAM of the system we are to design. u The aim of this diagram is to identify the INPUTS and OUTPUTS of the system - both for you the designer and for the customer as well. Discuss the design with the customer to ensure that this is what is desired (required).

21. BLOCK DIAGRAMS: Some Homespun Philosophy u There needs to be some method of “sketching a solution on the back of an envelope”. u This is used to discuss the design with the customer and the other members of the design team. u Show ALL the INPUTS and OUTPUTS. When we come to sequential designs, this includes the clock signal.

22. BLOCK DIAGRAMS: Some Homespun Philosophy u In practice, have the customer agree to this specification. Everything which follows depends upon this specification - if it is wrong then all your design efforts are wasted. u These basic ideas apply to any work you do as an engineer - ensure that the customer of your services knows what you are doing and what you have assumed.

23. Step 2: Label the Inputs u We usually use acronyms for the names of the inputs and outputs. This saves typing, but may obscure the significance of a signal. Choose the acronyms carefully. u In this case, let us make the following assignments: –S1 for hall switch 1. –S2 for hall switch 2. –Z for the output to the light fitting. Z is the conventional symbol used to signify an output.

24. Solution Step 3: Draw Up the Truth Table u TRUTH TABLES –These are the single most important item you will learn about in digital design. –Industrial designers VERY RARELY USE K- MAPS!!!! –K-Maps are a useful tool with which to gain experience in logic design, and to solve VERY SIMPLE minimization problems. –“Real Designers” use CAD packages on computers to perform logic minimization.

25. TRUTH TABLES u For combinational circuits, we need to have a standard manner in using truth tables: u We usually enter the input combinations in increasing numerical value, start at the value 000...00 and working up to 111...11 u That is, we enter the values systematically.

26. Initial Table Layout Note that the input entries are made first, and placed in increasing numerical order.

27. Complete the Truth Table u When both switches are off the light is off. u When either switch is on, the light is on. u When both switches are on, the light is off.

28. Step 4: Simplify the Truth Table u In this example, we were asked to simplify the truth table, if possible. u From your last course, you learnt of two possible techniques to simplify the truth table: –express the truth table as a (set of) symbolic equations, and use the laws of Boolean algebra to simplify the equation. –map the truth table onto a suitable (set of) K-map(s), and use the relevant techniques to simplify the truth table. u In practice, K-maps are always a simpler tool than symbolic equations, so that is what we use here.

29. K-Map Realization Sum of Products u From previous courses, you will realize that there is nothing further that we can do to reduce the number of terms in the truth table, assuming the Sum of Products (SOP) realization.

30. Solution u We accept this as the requested solution to our original design request.

31. Circuit Realization This circuit is called a two- level AND-OR realizing the given function. It is also called SOP - Sum of Products S1 S2’ S1’ S2 The same circuit can be realized can be realized with single EXOR gate with single EXOR gate

32. Circuit Realization with EXOR S1 S2

35. Karnaugh Maps

41. Minterms and Maxterms

43. Karnaugh Map1 1 1 11 1 1 1 1 1 0 0 00 0 0 True minterm False minterm Gray Code Gray code provides that the adjacent geometrically cells (minterms) are adjacent in sense of Hamming distance, they differ in one Boolean value only Natural number of the cell

44. The Next Step u Draw circuit. u Produce a schematic. u Test circuit. u Fix bugs, and update documentation. u Produce PCB. u Test... u Package u Check with customer again! u Get Paid!!!!!!!!!

45. Karnaugh Map Sum of Products Logic Draw and analyze the schematics The cover shown here is: X’Y’+X’Z’+ W’Y’Z+ W’XY+YZ’ This cover is not minimal

46. Karnaugh Map A better cover has the following primes: +X’Y’ (essential) + YZ’ (essential) +W’XZ(non -essential) Now you can prove that this cover is exact minimal solution Observe that the grey prime is now redundant (X’Z’)

47. INTRO: Covering, set covering, unate covering

48. EXOR and ESOP Minimization Intro

49. Karnaugh Map1 1 1 11 1 1 1 1 1 Exclusive Sum of Products Logic Draw and analyze the schematics Even/Odd Covering Exclusive Sum of Products Logic ESOP is the following: W’Y’  YZ’  W’Z  W’X’Z

50. 1 1 1 11 1 1 1 1 1 Exclusive Sum of Products Logic This is the best ESOP and in this case also the same groups are used in the best SOP. This is because the groups are disjoint. Improvement: W’Y’  YZ’  W’Z  W’X’Z = W’Y’  YZ’  W’Z(1  X’)= W’Y’  YZ’  W’ZX

51. Short Review of Exor Logic u A  A = 0 u A  A’ = 1 u A  1=A’ u A’  1=A u A  0=A u A  B= B  A u A B = B A u A(B  C) = AB  AC u A+B = A  B  AB u A+B = A  B when AB = 0 u A  (B  C) = (A  B)  C u (A B) C = A (B C) u A+B = A  B  AB = A  B(1  A) = A  BA’ These rules are sufficient to minimize Exclusive Sum of Product expression for small number of variables We will use these rules in the class for all kinds of reversible, quantum, optical, etc. logic. Try to remember them or put them to your “creepsheet”.

52. 1 1 0 10 1 0 0 0 0 0 0 00 1 1 Natural number of the cell This ESOP is : W’X’  YZ Learn how to design graphically such solutions

53. To Remember

54. What should you review for next time? u Please review the Kmap, implicants and covering from any undergraduate textbook such as Roth or Katz u Review basic Boolean algebra, De Morgan rules, factorization and flip-flops (D,T,JK). u You should be able to take arbitrary Kmap of 5 variables, truth table, netlist or expression and convert it to a truth table or Kmap. u Next you should be able to minimize it and draw a schematic with gates such as EXOR, NAND, NOR, etc. u You should be able to reformulate problem expressed in English as a Boolean minimization or decision problem. u SOP and ESOP logic and circuits. u These are the minimum information to start practical design problems.

55. Homework u Generate a random, but rather complex (not trivial) function of four variables. u Draw the Kmap for this function u Find the minimal ESOP. The function should be selected in such a way that the minimal ESOP will have four product terms, not trivial and the terms should be not disjoint. Minimize both graphically and algebraically. u Draw the circuit using standard logic gates such as AND, NOT and EXOR for this circuit. u For comparison, find the minimal SOP (using set covering) for this function. Draw the circuit.

56. What should have we just learnt? u As a designer, we need a systematic approach to designing. u We need ensure that the customer agrees to the product we intend to design. u This involves many interactions with the customer to ensure that the final product will be accepted. u We need sufficient documentation to ensure that, in the event of a dispute and threat of non-payment, we have SIGNED documents which show the customer agreed to everything we did. u Do no more than you will get paid for! That is, no extras that YOU think the customer might like.

57. Please review u Karnaugh Maps (Kmaps, for short) for 2,3,4 and 5 variables. u The adjacent cells - geometrically and in the sense of Hamming distance. u Enumeration of cells (minterms) u Don’t care minterms and how to use them u How to find prime implicants u How to find Sum-of-Products (SOP) Covers of sets of true minterms with prime implicants. u What are essential prime implicants and distinct vertices. –Distinct vertices are minterms that are covered by only one prime –Essential primes are primes that cover distinct vertices

58. What should you review? u Review basic Boolean algebra, De Morgan rules, factorization and flip-flops (D,T,JK). u You should be able to take arbitrary Kmap of 5 variables, truth table, netlist or expression and convert it to a truth table or Kmap. u Next you should be able to minimize it and draw a schematic with gates such as EXOR, NAND, NOR, etc. u You should be able to reformulate problem expressed in English as a Boolean minimization or decision problem. u These are the minimum information to start practical design problems.

59. For Advanced Students u If it is too easy, do not worry. u The class is for everybody. u I will go fast through repetition material. u Quite advanced material will soon appear.

60. Important for this year 1. Memristors and IMPLY 2. TANT networks 3. Negative Gate networks 4. Bi-Decomposition 5. AC decomposition 6. Trees of NANDs 7. ESOP, RM, PPRM, AND-OR-EXOR circuits 8. Systolic Processors 9. Data Flow 10. Image Processing Processors

61. Sources Some slides come from various sources, including Adam Postula, Mark Schulz and U.C. Berkeley