1. Abdulmotaleb El Saddik Prof. Dr.-Ing., FIEEE, FCAE University Research Chair ELG 4913F ELG 4913F Electrical Engineering Design Project II www.mcrlab.uottawa.ca

2. Course Description Applying previously acquired theoretical and experimental knowledge and skills from mathematics, basic sciences, engineering sciences and complementary studies, a team of students will pursue the design, implementation and validation of a significant electrical engineering system to meet specific needs. The work carried out during the second term will represent the second iteration of the product design and will focus on implementation and testing while involving significant performance analysis, project management and risk mitigation. Deliverables include a fully integrated and operational system prototype demonstration, written documentation and presentations in class. Work is guided by a professor, but is performed for a 'customer' entity, who must be satisfied with the team's demonstration of product’s features and functionalities

3. Lecture Lecture Schedule ◦Monday: 14:30 – 16:00 ◦Room: Desmarais Building (DMS)Room: 8161 Website ◦Blackboard lean ◦Students are required to check the course website frequently

4. Tentative Workload and Evaluation Lectures will serve as management meetings to ensure proper achievement of all components of the course and provide direct feedback to the teams. Group discussions and presentations will emphasize on various aspects of design, project planning, development, management, and on intellectual property.

5. Tentative Workload and Evaluation The team will continue to work on the same projects that were defined in ELG4912 with the goal to reach a fully integrated and functional prototype at the end of the term, while starting from the components designed and built in the previous term. Significant changes in the nature of the project are subject to the professor’s approval and are not encouraged.

6. Tentative Workload and Evaluation Two lab sessions are scheduled every week. They will provide students with time to integrate the components of their design, and to proceed with the necessary validation stages. The electronics lab will provide students with the opportunity to perform hands-on work with various devices that they already selected to use in their design. Students MUST attend the Management Meetings (as indicated by the professor on a weekly basis), and both Lab Sessions every week. The weekly lab sessions will be under the supervision of a TA. Attendance will be monitored.

7. Important Dates Individual Participation (10% of the final mark): Individual mark includes participation in the Lab (Lab attendance) and update on status of the project on Sept. 16, 2013 during the lecture. *Late submissions are NOT accepted. No exceptions!

8. Important Dates Midterm Progress Report (15% of the final mark): (deadline: Oct. 23, 4:00PM) The midterm will be in the form of a progress report. The report should show the teamwork as well as each member’s contribution up to the midterm date. The report should be submitted to the TA no later than Oct. 23, 4:00PM. The midterm reports will be discussed individually with each team member, during the scheduled lab)

9. Important Dates Project presentation (20%): (schedule: Dec. 2 & 3)This will be a presentation of the final design and validation of the project. The presentation will be conducted in front of the evaluation committee and with the attendance of all the course students and any other students wishing to attend. Each member of the team will have to talk about his or her own contribution to the project. Team members will be evaluated individually based on their personal performance.

10. Important Dates Final Prototype Demonstration (35%): (schedule: Dec. 2 & 3)After the presentation of the project, all team members are required to make a demonstration of the project in front of the examining committee. This demonstration will show the actual implementation of the design, how it works, and the results achieved. The mark given on the demonstration will be assigned equally to each member of the team

11. Important Dates Final Design and Validation Report (20%): (deadline: Dec. 10, 4:00 PM) This will be a comprehensive formal report detailing the background of the work conducted, the design methodology, the design diagrams, the analysis of results obtained, and the conclusion and recommendation of further studies. It is expected that each team member underlines his/her personal contribution to the project. The mark given on the report will be assigned equally to each member of the team.

12. Most 'First Class' students get technical seats, some become Doctors and some Engineers Harsh Reality The 'Second Class' passed, pass MBA, become Administrators and control the 'First Class' The 'Third Class' passed, enter politics and become Ministers and control both Last, but not the least, The 'Failures' join the underworld and control all the above

13. Fall 2008, Mohamad Eid ELG 5121 / CSI7631 Thank You! متشکرم

14. (c) Multimedia Communications Research Laboratory (MCRLab) http://www.mcrlab.uottawa.ca