1. Power Distribution for the LAr calorimeters for the HiLHC
Marco Riva
Università degli Studi di Milano
on behalf of the INFN-APOLLO collaboration
M. Alderighi(1,6), M. Citterio(1), M. Riva(1,8), P. Cova (3,10), N. Delmonte(3,10), A. Lanza(3), R. Menozzi(10), A. Paccagnella (2,9), F. Sichirollo(2,9), G. Spiazzi(2,9), M. Stellini(2,9), S. Baccaro(4,5), F. Iannuzzo(4,7), A. Sanseverino(4,7), G. Busatto(7), V. De Luca(7)
(1) INFN Milano, (2) INFN Padova, (3) INFN Pavia, (4) INFN Roma, (5) ENEA UTTMAT, (6) INAF, (7) University of Cassino, (8) University of Milano, (9) University of Padova, (10) University of Parma

2. Outlines APOLLO project:
Power Distribution Proposal for the LAr Calorimeter
Design and preliminary tests of the Main Converter and PoL
Engineering Issues:
Thermal Design;
Magnetic Materials with High saturation;
Analog/Digital/Power Devices selection:
Behavior in radiated environment
Goodmorning
December 6, 2011
sLAr Electronics Meeting - M. Riva

3. The APOLLO Project: LV Power Supplies For The Next High Energy Physics Experiments
Full replacing the present systems whose design dates from early 2000 years: new and improved design possibility;
Minimization of power loss in cables used for carrying current from PS distributors to the front-end of detectors push the distributors as close as possible to the front-end;
New and more severe environment requirements:
Increased rad-hard performance, because of the increased luminosity of accelerators;
Increased B-tolerance of systems getting closer to detectors and magnets;
Better reliability and controls, in order to reduce access time and increase the overall detector efficiency;
Avoiding industrial intellectual property, trying to implement the CERN Open Hardware policy;
The main goal of the APOLLO project is to investigate and propose a LV Power Supplies Distributed Architecture suitable for the Next High Energy Physics Experiments.
In order to define the new needs it worthwhile underline the present increased demand of integration of the electronics with detectors at the design level, to avoid both mechanical and electrical criticalities:
This new trend has some drawback and, in fact, it requires:
a careful design in terms of EMC;
Necessity of rad-hard devices, so to place modules in the experimental caverns;
Necessity of B-tolerant systems, to be able to place them close to detectors;
The activities of the APOLLO project used as test case the power distribution architecture of the LAr calorimeter.
December 6, 2011
sLAr Electronics Meeting - M. Riva

4. Power Distribution Architecture for LVPS: Present status
19 Low drop-out regulators/FEB
Just to mention this slide reports the present Power distribution architecture adopted for the Lar calorimeter used as test case example. We can see ….
ATLAS Experiment Power Distribution System for the FEB of the LAr Calorimeters
December 6, 2011
sLAr Electronics Meeting - M. Riva

5. Power distribution architectures
Centralized Power Architecture (CPA):
An isolated DC/DC converter generates the whole set of regulated DC voltages (±12V, ±5V and +3.3V) supplying the circuit subsystems.
Decentralized Power Architecture:
The low voltage distribution is moved close to the load by means dedicated converters;
Distributed Power Architecture (DPA):
A single intermediate DC bus (+48V or +12V) is generated by a main converter
Intermediate Bus Architecture (IBA)
In addition to the generation of a main voltage bus (48V-76V), a second set of BUS voltages are provided (8V-14V). Lower voltages are given by the point-of-load converters.
Spot Power Architecture
Intermediate solution between CPA and DPA. In addition to the voltage bus typical of DPA, one or more voltage lines supply the circuits directly.
Factorized Power Architecture (FPA)
A “factorized” bus (26V-55V) not stabilized and not galvanic insulated supply the POL by means dedicated converters.
High number of long connection cables (penalty in volume and weight)
Low flexibility
High losses mainly in unique hot spot + losses in linear regulator LDO
Possible cross-talk effect between the power supply.
High Voltage Drop
Improvement in the efficiency
Independent control of the different loads
Not optimal solution considering weight and size
High number of devices
Low Voltage Drop
Optimized Voltage Drop
High static regulation and improvement of the dynamic performances
(the impact of the series resistance and inductance is reduced)
The DPA approach benefit from increased efficiency, low size and weight
Several types of power supply distribution architectures, specific devoted to servers farm, high performance PCs, have been introduced in the last decade and are today employed.
Their electrical characteristics are determined by the evolution of digital circuits, whose switching frequencies moved to the GHz range and supply voltages reduced down to the level of 1V with a correspondent increase of the current demand.
Centralized Power Architecture (CPA):
it's based upon an isolated DC/DC converter, that generates the whole set of regulated DC voltages (typically ±12V, ±5V and +3.3V) supplying the circuit subsystems.
Distributed Power Architecture (DPA):
A single intermediate DC bus (typically +48V or +12V) is generated by an off line converter, consisting in a Power Factor Converter (PFC) and a main DC to DC converter. The bus voltage is reduced to lower levels by means of point-of-load DC/DC converters located directly on the motherboards close to the loads.
Intermediate Bus Architecture (IBA)
In addition to the generation of a main voltage bus, as in the DPA but typically higher (48V-76V), a second set of PCB bus voltages is provided (8V-14V). Then lower voltages are given by the point-of-load converters.
Spot Power Architecture
It is an intermediate solution between CPA and DPA. In addition to the voltage bus, typical of DPA, one or more voltage lines supply the circuits directly.
Factorized Power Architecture (FPA)
A “factorized” bus (26V-55V) not stabilized and not galvanic insulated it is used to supply the POL by means of dedicated high frequency isolated converters. (VTM: Voltage Transformer Module; PRM: Pre-Regulator Module)
The studies didn't show a clear evidence of a best solution over the others leaving the choice of the more suitable to the designers.
Factorized Power Architecture
December 6, 2011
sLAr Electronics Meeting - M. Riva

6. The APOLLO proposal – System architectures
Upgrade from “Centralized Power Architecture” to
“Distributed Power Architecture”
Rationalization of the number and level of the voltages required by FEBs
only few intermediate voltages must be supplied (one or two)
loads must be served by PoLs regulators
Possibility of adopting non-traditional topologies:
modular approach (possible benefit for other detectors)
higher switching frequency
optimized design of magnetic devices
minor losses and heat
reduced voltage across devices
In order to face the new exigency of electrical power request, high reliability and efficiency of the upgrade phase the APOLLO proposal consists in the developing of a Distributed Power Architecture constituted by:
December 6, 2011
sLAr Electronics Meeting - M. Riva

7. Proposed Power Distribution Scheme
CRATE
FEB #3
POL
LDO Converter
FEB #2
FEB #1
PoL
niPoL Converter
Main
DC/DC
Converter
280 Vdc
Regulated DC bus
The movement of the power distributors close to the detector reduce the power converter complexity but increase the design of the whole system with few critical active devices…
12Vdc5%
High DC conversion ratio converters
PoL = Point of Load
48Vdc5%
December 6, 2011
sLAr Electronics Meeting - M. Riva

8. Distributed Power Architecture proposal for the Moun Detector
Case study:
The DC/DC Power Converter adopted for the Moun Detector could benefit from the modular approach adopted in LAr calorimeter.
Muon Detector
POL
LDO Converter
Chamber #1
PoL
niPoL Converter
Chamber #3
Chamber #2
Main
DC/DC
Converter
280 Vdc
The standardization of the MC modules (they are not more connected to the Loads requirements) makes possible their re-use in other power distribution architectures:
Characteristics:
Main isolated converter with N+1 redundancy
High DC bus voltage (12V or more)
Distributed Non-Isolated Point of Load Converters (niPOL) with high step-down ratio, installed on-chamber and high B-tolerant (more than 2T) coreless inductance in air
Regulated DC bus
December 6, 2011
sLAr Electronics Meeting - M. Riva

9. High radiation & magnetic field tolerance
Critical problems
Electromagnetic immunity of the front-end electronics to the switching converters
Converters Design (Main and PoLs)
Number and levels of intermediate voltages
How many? Positive and negative?
Which levels? High for loss reduction or lower for a reasonable POL design (voltage ratio)?
Redundancy N+1 (single failure tolerance)
Modular approach: number of modules Vs total power oversizing
Thermal design
Power losses distribution
Analog/Digital/Power Devices
Active switches selection
Power and voltage level
Switching frequency
MOSFETs, SiC, GaN
Analog/Digital Controllers
PWM Controllers
Drivers
Signal Isolators
FPGAs
Design of magnetic parts
Coreless devices
Low permeability cores
Thermal analysis
Water cooled
In order to fully investigate the criticality of the proposal some main items has been individuated :
In the following we discuss the approaches followed by APOLLO
High radiation & magnetic field tolerance
December 6, 2011
sLAr Electronics Meeting - M. Riva

10. Preliminary FEB EM Noise Tolerance Tests with PoL Converter
Jim Kierstead, Sergio Rescia, Hucheng Chen, Francesco Lanni (Brookhaven National Laboratory)
LTM4602 – 6A High Efficiency DC/DC μModule
Complete Switch Mode Power Supply
Wide Input Voltage Range: 4.5V to 20V
6A DC, 8A Peak Output Current
0.6V to 5V Output Voltage
1.5% Output Voltage Regulation
Up to 92% Efficiency
Output Over Voltage Protection
IR3841 – Integrated 8A Synchronous Buck Regulator
Greater than 96% Maximum Efficiency
Wide Input Voltage Range: 1.5V to 16V
Wide Output Voltage Range: 0.7V to 0.9*Vin
Continuous 8A Load Capability
Programmable Switching Frequency up to 1.5MHz
Programmable Over Current Protection
Thanks to the cooperation with BNL
EM tolerance of FEB on POLs emission have been tested
December 6, 2011
sLAr Electronics Meeting - M. Riva

11. Summary of the preliminary EM tests
Irradiated noise of PoL Converters
Outside FEC:
Negligible effect on coherent noise
Inside FEC:
Shielding is necessary to achieve good noise performance inside FEC
Conducted noise of PoL Converters
December 6, 2011
sLAr Electronics Meeting - M. Riva

12. The APOLLO proposal - MC
The Main Converter is based upon a DC-DC Phase Shifted Converter well suited for multi-outputs, or-ed connection and constant load supply (single pole dynamic).
The whole unit is constituted by 3 modules connected in parallel:
Vin=280 V
Vout= 12V
Pout= 1.5 kW
fs=100kHz
The supervisor and protections are demanded to an external interface:
current Sharing
start-up control/failure
clock, phase shift between the modules, Alarms
December 6, 2011
sLAr Electronics Meeting - M. Riva

13. Switch In Line Converter
Merits
High switching frequency
Fixed switching frequency
Soft switching commutation
(use of parassitics elements: leakeage inductance)
Single pole dynamics
Well suited for multiple outputs
Suited for or-ed outputs
Reduced MOS drain-source voltage
Non-isolated feedback available
The topology proposed is shown in the figure.
The original circuit was introduced few years ago by the electronic section of the university of Milan and it gained popularity since it was used in the power distribution system on-board the international space station for the non-US apparatus.
Due to the particular disposition of the active switches it is called "Switch In Line Converter" (SILC).
The circuit consists in the series connection of two half bridge converters (lower HB and upper HB) controlled by a PWM phase shifted operation.
Each half bridge switches with 50% duty-cycle. The power flowing is controlled by the shift-delay between the upper half bridge commands and the lower one.
During the on transition of each MOSFET a resonance between the inductor L and the parasitic capacitors allows soft switching (ZVS)
Drawbacks
High drain current levels
High number of large capacitors
December 6, 2011
sLAr Electronics Meeting - M. Riva

14. How SILC topology works
A short overview of the basic operations of the circuit is reported.
Reference is made to steady state conditions and to the ideal switching sequence
Connections in parallel are allowed because the SILC power cell acts like a current controlled generator.
The transfer power occurs during the time slots putted into evidence by shadow area.
The input voltage partition due the series connection of the half bridges, reduces the voltage stress of the MOSFETs and the voltage gap to span during the resonant transition.
This allows stretching the soft-switching persistence for a wider power range as compared with other PWM phase shifted topologies.
The initial status, at t =t 0- , of the switches is: S1 OFF, S2 ON, S3 OFF, S4 ON.
At t=t0+ S4 turns OFF; the current IL flows through Cp4 and Cp3 during the soft-switching interval until D3 clamps; S3 turns ON at t=t1- .
Then, since the voltage across L is -2V0 , IL decreases and reverses its polarity until it reaches the values max , -IL at t=t2−, when S2 turns OFF and the output rectifiers too. Current balance in the transformer implies that It1+ItL=It1-ILmax=0, hence max , It1=ILmax.
Another resonant voltage clamped transition, identical to the previous one, occurs at node 1. Switch S1 turns ON at t=t3- after clamping of D1. From t3 t4 the current IL remains constant; in this interval the Kirchoff law implies IL+IT1=I0, where IO is the output current reflected at the primary side of the transformer. When S3 switches OFF (t=t4-), the second half period begins and it exactly mirrors the first one.
The period ends at t=t8+=t0+T. IL t
December 6, 2011
sLAr Electronics Meeting - M. Riva

15. Power Transformer Design
The transformer is constituted by 2 primary windings and 1 low voltage secondary winding (5:5:1)
 traditional windings
 planar structure X
The whole transformer has been divided in 4 subsystems
Each subsystem consists by 10 turns for each primary windings and 2 turns for the center tapped secondary.
The secondary has been realized by means of the parallel connections of 2 windings in order to reduce the output leakage inductance.
December 6, 2011
sLAr Electronics Meeting - M. Riva

16. “Subtransformer” Design
The windings of each subsystems are realized by means of a 22 layers PCB
4 layers
Thermal Layer for heat dissipation
4.71mm
22 layers
10 layers
2 turns for every layers
4 layers
UL94V-0
December 6, 2011
sLAr Electronics Meeting - M. Riva

17. Single Module View 315 60 130 December 6, 2011
sLAr Electronics Meeting - M. Riva

18. Experimental Tests Open loop operation:
Ch1) gate-source command of the lower MOS
Ch2) inductor current
Ch3) M1 drain-source voltage
Ch4) M3 drain-source voltage
Efficiency Vs Output Power
December 6, 2011
sLAr Electronics Meeting - M. Riva

19. Dynamic measurement: Gloop
Control to Output (Gloop) dependency from output power
December 6, 2011
sLAr Electronics Meeting - M. Riva

20. Design of PoL Converter: Synchronous Buck
The requirement of high B (2-4T) makes mandatory the use of coreless solution (inductance in air);
The value of the inductance is limited to few 100nH;
High current ripple (DiLpp > 2IL) -> High C in order to limit the output ripple
High switching frequency
December 6, 2011
sLAr Electronics Meeting - M. Riva

21. Multiphase Synchronous Buck (interleaved)
SL1
SH1
SL2
SH2 - + ug uo
iL1
iL2
iLtot
Switches command delayed of TS/n with n number of phase (2 in figure)
iL1
iL2
iLtot
Io/2 Io
Fsw
2·Fsw t
TS/2 TS
SH1
SH2
Limitation of the output ripple
December 6, 2011
sLAr Electronics Meeting - M. Riva

22. Current Ripple Cancellation
Vo=1.3 V
12 V
5 V
Input voltage 1
D=0.5 for the best cancellation effect
0.9
0.8
0.7
Two
phases
0.6
Ripple Ratio
0.5
0.4
0.3
0.2
0.1
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9 1
Duty cycle 1
0.9
0.8
The interleaved solution can benefit from a current ripple compensation which requires however high number of phase and low duty cycle proportional to the voltage ratio
0.7
Four
phases
D=0.25, 0.5, for the best cancellation effect
0.6
Ripple Ratio
0.5
0.4
0.3
0.2
0.1
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9 1
Duty cycle
December 6, 2011
sLAr Electronics Meeting - M. Riva

23. Interleaved Buck with Voltage Divider - IBVDS1 S2 S3 S4 L1 Co R C1 L2 Ug uo + -
uC1 i1 i2
Phase shift TS/2
D<50% Uo = UgD/2 e UC1 = Ug/2
D>50% Uo = UgD2 e UC1 = Ug(1-D)
December 6, 2011
sLAr Electronics Meeting - M. Riva

24. How IBVD works: D < 0.5 0 < t < DTS iL2 iL1 iC1 iL1+iL2 S1 S2
-iL1 S1 S2 L1
iL1 + Ug + uo
uC1 C1 S4 Co Ro
iC1 L2
iL2 S3
0 < t < DTS
December 6, 2011
sLAr Electronics Meeting - M. Riva

25. How IBVD works: D < 0.5 DTS < t < TS/2 iL2 iL1 iC1 iL1+iL2 S1
-iL1 S1 S2 L1
iL1 + Ug + uo
uC1 C1 S4 Co Ro
iC1 L2
iL2 S3
DTS < t < TS/2
December 6, 2011
sLAr Electronics Meeting - M. Riva

26. How IBVD works: D < 0.5 TS/2 < t < TS/2+ DTS iL2 iL1 iC1
-iL1 S1 S2 L1
iL1 + Ug + uo
uC1 C1 S4 Co Ro
iC1 L2
iL2 S3
TS/2 < t < TS/2+ DTS
December 6, 2011
sLAr Electronics Meeting - M. Riva

27. How IBVD works: D < 0.5 TS/2+ DTS < t < TS iL2 iL1 iC1
-iL1
iL1
iL2 L2 L1 S2 S4 S1 S3 Ug uo Ro Co C1 +
iC1
uC1
TS/2+ DTS < t < TS
December 6, 2011
sLAr Electronics Meeting - M. Riva

28. How IBVD works: D < 0.5 iL2 iL1 iC1 iL1+iL2 iL1 iL2 L2 L1 S2 S4 S1
-iL1
iL1
iL2 L2 L1 S2 S4 S1 S3 Ug uo Ro Co C1 +
iC1
uC1
December 6, 2011
sLAr Electronics Meeting - M. Riva

29. Interleaved Buck with Voltage DividerS1 S2 S3 S4 L1 Co R C1 L2 Ug uo + -
uC1 i1 i2
High step-down ratio
Reduced current in each inductor
Increased of the equivalent frequency in the output filter
Reduced switch voltage stress (Uin/2):
ZV switch turn-on
Interleaved operation with automatic current sharing and ripple cancellation
High number of passive elements
High complexity of the control circuit
December 6, 2011
sLAr Electronics Meeting - M. Riva

30. IBVD: experimental characterization
Input Voltage: Ug = 12 V
Output Voltage: Uo = 2.5 V
Output Current: Io = 3A
Size: L = 6cm, W = 4.2cm
output
Single buck
input
Cin = 100nF + 10mF
Co = 2x47nF + 2x47mF + 2x10mF
L = 90nH – 30mW
Q1,2 = 2xIRF8915
IBVD
Cin = 100nF + 10mF
Co = 2x47nF + 4x2.2 mF
C1 = 2x470nF (1206)
L1 = 161nH – 58mW
L2 = 169nH – 63mW
S1,4 = IRF8915
fs = 1MHz
December 6, 2011
sLAr Electronics Meeting - M. Riva

31. Efficiency comparison @ fs = 2MHz
December 6, 2011
sLAr Electronics Meeting - M. Riva

32. High Current IBVD Input Voltage: Ug = 12 V Output Voltage: Uo = 2 V
Output Current: Io = 20A
Switching Frequency: fs = 280 kHz
2.2 mH (iron core inductance)
Size: L = 7cm, W = 3.5cm Co C1
Cin L1 L2 S1 S3 S4 S2 S1 S2 S3 S4 L1 Co R C1 L2 Ug uo + -
uC1 i1 i2
Control circuit on the other side of the PCB
December 6, 2011
sLAr Electronics Meeting - M. Riva

33. IBVD IBVD Efficiency Output current [A] 0.78 0.8 0.82 0.84 0.86 0.88 510 15 20
IBVD
Efficiency
Output current [A]
December 6, 2011
sLAr Electronics Meeting - M. Riva

34. Thermal Modeling – Top-Down Approach
Water cold plate
System Level
boards and cold plate position
Board Level main heating devices modules layout heating convection and conduction
Device Level package definition heating exchange between single components
December 6, 2011
sLAr Electronics Meeting - M. Riva

35. Modeling (and Simulations) @ System Level
3D Thermo-fluidynamic FEM of working and faulty converters
Liquid Cooled Chassis:
2 mm 1510 steel case containing 3x1kW main converter modules cooled by cold plates
Outiside crate
Liquid
Internal surface
18°C
29°C
35°C
Outlet water temperature required 25°C
Maximum cold plate internal temperature: 35°C
(The power losses distribution have been supposed uniform !)
December 6, 2011
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36. Simulation in case of failure
3D Thermo-fluidynamic FEM of working and faulty converters
Liquid Cooled Chassis:
2 mm 1510 steel case containing 2x1.5kW main converter modules cooled by cold plates
Outside crate
Liquid
Internal Surfice
18°C
45°C
34°C
Maximum cold plate internal Temperature 45°C
External Wall 18°C  GOOD (required: 18 °C)
December 6, 2011
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37. Modeling @ Device Level
Packages: TO-220 and D2PAK
Device Model
Layers considered:
(1) FR (2) IMS (3) FR4+Slcn (4) FR4 with thermal vias
M. Bernardoni et al., ESREF’09, Arcachon (F), 5-9 ott
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38. Simulation of different packages
(1) FR4
(2) IMS
(4) Th. vias
(3) FR4+Slcn
December 6, 2011
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39. Thermal modeling of Planar Transformer
Physical dimension and material definition
Thermal simulation
Building mesh
December 6, 2011
sLAr Electronics Meeting - M. Riva

40. Modeling @ Board Level: the MC prototype
Rif. N°
Device
PD [W] 1
MOSFET MC (TO247) 5 2
Planar Trasf. - Core
100 3
Planar Trasf. – Windings 65 4
Diode (ISOTOP) 35
Inductor 6
Cu traces for the secondary 7
MOSFET AUX (TO247)
0,1 8
AUX Transf. – Core
0,5 9
AUX Transf. – Windings 10
AUX MOSFET (D2PAK) 11
Capacitors
<0,1
Total Power Loss
217
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41. FE Physical definition and meshing
Mesh with freedom levels
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sLAr Electronics Meeting - M. Riva

42. Simulation Results
Maximum temperature acceptable (considering Text = 28 °C)
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sLAr Electronics Meeting - M. Riva

43. Thermal measurements Vs simulations
The experiment has been done with air cooling system 
Pout = 1.2 kW
(Iout  100 A)
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44. Planar Transformer Tests in Bstat
The behavior of the planar transformer and in particularly of the low permeability magnetic core (Koolm by Magnetics) has been tested in condition close to the normal operation : Vcc=70, fs=100kHz.
December 6, 2011
sLAr Electronics Meeting - M. Riva

45. Experimental Set-up
Zoom of the magnet gap at the INFN-LASA test facility
Several values of magnetic field have been used to test the transformer:
Bstaz=[789, 1295 , 1533, 1987, 2247 e 2591] Gauss.
The external Bstaz influenced the normal operation in grater way when approaching to the saturation
December 6, 2011
sLAr Electronics Meeting - M. Riva

46. Transformer behavior in stationary Magnetic Field
11/16/2011 46
Bstat. 789 Gauss
Bstat Gauss
orange = primary winding voltage
blue = secondary winding voltage
magenta  = primary winding current
green = snubber current (proportional to the switching losses).
December 6, 2011
sLAr Electronics Meeting - M. Riva

47. Soft ferromagnetic materials for enhanced inductor cores
Optimization of the inductor core material for DC-DC switching power supplies
Need of high of reliability magnetic cores of devices for extreme condition environments:
High immunity to radiations
High magnetization field and low coercive field
High Br Low Hc
Higher switching frequencies of the DC-DC converters
Smaller dimensions of the inductors
December 6, 2011
sLAr Electronics Meeting - M. Riva

48. FeSi compound Better high-frequency inductor core performance
Avoidance of magnetostriction phenomena
Increase anisotropy
Enhanced soft magnetic properties
Specific activities are addressed to obtain a ferromagnetic nucleus able to produce high magnetic field with limited current stimulations. The base elements consist in a mixture of Fe and Si powders blended in precise ratio (percentage of organic additives, and blending methodology are key points) in order to make a ferromagnetic compound injection moulded in test sample.
Starting from power
Composition: Fe-6.8%Si
Grain size: micron
December 6, 2011
sLAr Electronics Meeting - M. Riva

49. Fabbrication process Metal Injection Moulding (MIM)
FeSi powder + polymer binder (“green” material)
Debinding at 600°C
Sintering at 1260°C
December 6, 2011
sLAr Electronics Meeting - M. Riva

50. Challanges Cold ductility of such material makes its manufacture hard;
Use of a hydrogen atmosphere to avoid Fe oxidation during sintering;
Hard and time-expensive recipe tuning;
MIM parameters set: temperature of the material, of the cylinder and mould, pressure of injection, hold pressure, injection speed and screw feeding speed, time for the injection, time for hold pressure, time of cooling.
December 6, 2011
sLAr Electronics Meeting - M. Riva

51. Prototype radiation tests
The prototype has been exposed to a dose of 5 kGy
At a dose rate conditions of 100 Gy/h, during 2 days of exposure in the 24 hours
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sLAr Electronics Meeting - M. Riva

52. Preliminary Results I
Initial local fusion of the polymeric component and a less crystallinity
December 6, 2011
sLAr Electronics Meeting - M. Riva

53. Preliminary Results II
Detail of the polymeric ageing
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sLAr Electronics Meeting - M. Riva

54. The APOLLO proposal – Rad-hard devices
Seeking for power COTS MOSFETs radiation tolerant up to 10kGy and 1014/(s ∙ cm2) neutrons and protons:
many components, with Vd ranging from 30V to 200V and polarized in various configurations, were tested at the 60Co g ray source in the ENEA center of Casaccia, near Roma
same components were tested with a heavy ion beam, 75Br at 155MeV, at INFN Laboratori Nazionali del Sud in Catania
within the end of the year same components will be tested under neutrons, at the Casaccia nuclear reactor Tapiro, and under protons, at INFN LNS
Seeking for COTS controllers and FPGA radiation tolerant:
first irradiation was performed under 216MeV proton beam in Boston, at Massachusetts General Hospital facility, using some of devices irradiated in Italy. Other irradiation campaigns are planned at the same facilities in the next months
Results are still preliminary and under analysis.
Other irradiation campaigns are necessary in order to select good devices.
December 6, 2011
sLAr Electronics Meeting - M. Riva

55. Circuit set-up for g tests
Four parallel tests:
Vdd=0 and Vgg=const. (80%Vgg,nom)  sensitivity to the oxide bias
Vgg=0 and Vdd=const. (80%Vdd,nom)  sensitivity of the bulk (junction) of the device
Vdd=80%Vdd,nom and Vgg switching  sensitivity to the dynamic gate bias
three leads shorted  reference condition
Vgg=const.
Vdd=const.
switching
shorted
December 6, 2011
sLAr Electronics Meeting - M. Riva

56. Switching condition effect during radiation - 30V MOSFETs –
Prossima: Oxide damage
December 6, 2011
sLAr Electronics Meeting - M. Riva

57. Switching condition effect during radiation - 200V MOSFETs –
Different manufacturers
Device B1
December 6, 2011
sLAr Electronics Meeting - M. Riva

58. Asym./Sym. Switching Comparison
Prossima: DIFFERENT MANUFACTURERS
December 6, 2011
sLAr Electronics Meeting - M. Riva

59. Susceptibility to dose rate - 40Gy/h vs. 10Gy/h -
Prossima: DIFFERENT MANUFACTURERS
December 6, 2011
sLAr Electronics Meeting - M. Riva

60. VTH SiC JFETs Prossima: DIFFERENT MANUFACTURERS December 6, 2011
sLAr Electronics Meeting - M. Riva

61. Ron SiC - SiC JFETs - Prossima: DIFFERENT MANUFACTURERS
December 6, 2011
sLAr Electronics Meeting - M. Riva

62. Combined effects: g rays and Heavy Ions
Devices under test:
30V STP80NF03L-04
30V LR7843
200V IRF630
For each type of device 20 samples were tested, 5 for each dose value
(g rays at the ENEA Calliope Test Facility)
Measurements :
Breakdown VGS=-10V
Threshold VDS=5V
ON VGS=10V
Gate VDS=10V
Used doses:
I Gray
II Gray
III Gray
IV Gray
December 6, 2011
sLAr Electronics Meeting - M. Riva

63. The SEE experimental set-up
The current pulses
The IGSS evolution during irradiation
The device is in “OFF” state and biased at constant VDS and VGS voltages Cg Cd
50 W
1 MW
Vgs
Impacting Ion
DUT
Vds
Drain P + N _
Gate
Source
Body
Parameter Analyzer
Fast Sampling Oscilloscope
December 6, 2011
sLAr Electronics Meeting - M. Riva

64. The SEE experimental results
200 V Mosfet: IRF630
Device
TID
Bias Conditions during Irradiation
Drain Damage
Gate Damage
D21
0Gy
Vds=20V-110V vgs=-2V
Vds=100V-110V
D06
1600Gy
Vds=20V-70V vgs=-2V
Vds=60V-70V
D10
3200Gy
Vds=20V-50V vgs=-6V
Vds=40V-50V
D16
5600Gy
Vds=45V-50V
Vds=40V-45V
D17
9600Gy
Vds=20V-45V vgs=-6V
The increase of the ϒ-dose causes a reduction of the critical bias condition at which drain and gate damages appear
December 6, 2011
sLAr Electronics Meeting - M. Riva

65. MOSFETs Exposed to Protons
Only 200V MOSFETs (IRF 630, samples from two different manufacturers) were exposed
Proton energy: 216 MeV (facility at Massachusetts General Hospital, Boston)
Ionizing Dose: < 30 Krads
An “absolute” cross section will require the knowledge of the area of the MOSFET die which is unknown.
The results are still preliminary.
December 6, 2011
sLAr Electronics Meeting - M. Riva

66. MOSFETs Exposed to Protons
The number of SEB events recorded at each VDS was small
 less then 30 events for the ST
 less than 150 events for the IR devices
 Large statistical errors affect the measurements
The cross section at VDS = 150V (“de-rated” operating voltage) can not be properly estimated
Dependence from manufacturer
“Knee” not well defined
To effectively qualify the devices for 10 years of operation at Hi-LHC, the cross section has to be of the order of 10-17/ cm2, which puts the failure rate at <1 for 10 years of operation.
Proton irradiation campaigns with increased fluences and more samples are planned.
Work still in progress …
December 6, 2011
sLAr Electronics Meeting - M. Riva

67. GaN Devices for fast switching
High frequency, high voltage ratio PoL criticalities:
They must operate at low duty cycle (high voltage ratio);
The switching period is short and operations are achievable only with fast switching commutations;
GaN devices have the potential to switch ON-OFF in the MHz range
(related to the driving capability and the assembly techniques)
National Semiconductor
180W 1/8th Brick, Fully Regulated Converter
December 6, 2011
sLAr Electronics Meeting - M. Riva

68. Studies on GaN Devices
The tests adopt 40V and 200V GaN devices by EPC;
Some problems in driving and prepare the test circuit (soldering the components)
Electrical Characterizations are in progress
Air bubbles
X-rays for checking the solder quality
December 6, 2011
sLAr Electronics Meeting - M. Riva

69. Preliminary electrical charcterization
EPC GaN MOSFET
Preliminary electrical charcterization
VDC vc
DRIVER
DUT L
VCC + C1
iDUT
Measured DUT voltage and current during switching intervals
Rshunt = 85 mW
UGS [1V/div]
UDS [20V/div]
-IDS [1A/div]
Time [10ns/div]
UGS [1V/div]
UDS [20V/div]
-IDS [1A/div]
-poff(t)
Time [10ns/div]
Turn on Vcc = 100V, IDS = 0A
Turn off Vcc = 100V, IDS = 5A
December 6, 2011
sLAr Electronics Meeting - M. Riva

70. Conclusion Distributed Power Architecture has been proposed
Main converter (SILC topology)
Point of Load converter (IBDV topology)
Proper Magnetic Devices Design
Power Planar Transformer (new magnetic material)
Inductor in air
Thermal Design
Critical selection of components to proper withstand radiation
Controller, Driver and Isolator
FPGA for overall monitoring
MOSFETS
MOSFETS, both for MC and PoL have been selected and tested
Gamma ray
Heavy ions
Protons
Some results are encouraging, however more systematic validation is on-going
Novel devices based on SiC and GaN, are also under investigation
December 6, 2011
sLAr Electronics Meeting - M. Riva

71. Future Activities
Update the design of the MC and realize a new prototype;
Investigate the use of PoL made by CERN (F. Faccio) for high current loads;
Test the IBVD PoL converter directly on the FEBs;
Propose/Find radiation tolerant controllers
Selection of PWM
Custom made controller by using Analog Devices or FPGAs
December 6, 2011
sLAr Electronics Meeting - M. Riva

72. Schematic of the Single Module (1.5 kW)
Dual-threshold current controller
used to manage the capacitor charge and over load protection
Auxiliary Power Supply for start-up and under voltage protection
1.5 kW SILC Power Converter
Input voltage
280 V
Output voltage (MC)
12 V
Maximum power (MC)
1.5 kW
Switching frequency (MC)
100 kHz
Output voltage (AUX)
V1,V2,V3=12 V
V4=5 V
Maximum power (AUX)
20 W
Switching frequency (AUX)
200 kHz
Auxiliary Power Converter
December 6, 2011
sLAr Electronics Meeting - M. Riva