1. Lecture 111 Lecture 11: Lab 3 Overview, the ADV7183B Video Decoder and the I 2 C Bus ECE 412: Microcomputer Laboratory

2. Lecture 112 Objectives Introduce Lab 3 Describe the Analog Devices 7183B SDTV video decoder present on the Digilent VDEC1 board Discuss the I 2 C bus that you’ll use to configure the ADV7183B

3. Lecture 113 Lab 3 FPGAVideo Board VGA Out SDRAM PowerPC PLB SDRAM Controller SDRAM Controller VGA Controller VGA Controller ADC Controller ADC Controller ADC Chip DAC Chip Frame Buffer

4. Lecture 114 Lab 3 Checkpoint 1: Display static image on VGA –Software places image in frame buffer, VGA displays Checkpoint 2: Video capture, Part 1 –Implement YUV->RGB conversion –Display the full motion video stream at 640x480 resolution Checkpoint 3: Video capture, Part 2 –Implement the portion of the I 2 C protocol needed to write to the configuration registers in the ADV7183B video decoder

5. Lecture 115 LAB 3 Overview

6. Lecture 116 New Hardware: Digilent VDEC1 ADV7183B video analog to digital converter

7. Lecture 117 VDEC1 The Video Decoder 1 board (VDEC1) with the ADV7183B Video Decoder chip can digitize NTSC, PAL, and SECAM video signals. The ADV7183B automatically detects standard analog baseband television signals, and digitizes them with three 54MHz 10-bit ADCs. Output data can be sent to an attached system board in 8-bit or 16-bit YCrCb 4:2:2 format.

8. Lecture 118 ADV7183B Convert a variety of analog video input formats into 8-bit YUV digital Composite (lower quality) and S-Video input (higher quality) Supports many modes, including close captioned

9. Lecture 119 I/O Signals DVDD,AVDD,PVDD,DGND,AGND: Power/ground supplies AINxx, AGND: Analog video inputs P[0-15]: Digital video pixel outputs XTALx: external clock inputs OE#: Enables the pixel output bus RESET: Chip internal reset INTRQ#: interrupt request output LLCx: Line-locked system clock output HS, VS, FIELD: Synchronization output signals SDA, SCLK: Serial clock/data lines for I2C bus –Used to program/control chip ALSB: Jumper selectable I 2 C address This material is an overview only; learn to access and use manufacturers datasheets as posted on the ECE412 website.

10. Lecture 1110 Connections to XUP Board (1)

11. Lecture 1111 Connections to XUP Board (2)

12. Lecture 1112 I 2 C Bus Motivation Problem: Systems in which one or more microprocessors/microcontrollers control several integrated circuits becoming increasingly common Want common control interface to simplify design Need to limit number of signals required to keep part costs down Need flexibility –Variable number of devices on bus –Support for > 1 master device –Variable data rates I 2 C = Inter-IC Bus

13. Lecture 1113 Basic Architecture Two serial, bidirectional lines connect programming inputs of all devices Number of devices on bus limited only by requirement that total load be < 400pF Wire interface identical for master and slave devices SCLK (Serial Clock Line) SDA (Serial Data Line) Device 1 Device 2 Device 3 Device 4

14. Lecture 1114 Wired-AND Connection Pullup resistors pull each line to Vdd when not driven Any device can drive line by pulling to zero Devices don’t actively drive to one –Stop driving and let pullup handle

15. Lecture 1115 Implementing this Connection on FPGA Need to declare SCLK, SDA as inouts Use tri-state driver to drive each wire –When you want to drive a zero, enable tri-state and drive a zero –Otherwise, disable tri-state –Note that this can be accomplished by wiring the data input of the tri-state driver to zero and generating the appropriate control signals.

16. Lecture 1116 Bus Timing Asynchronous bus – not driven by a constant clock Base version of bus supports up to 100Kbits/sec data transfer –Fast version (supported by ADV7183B) allows 400Kbits/sec –“High Speed” version gets up to 3.4 Mbits/sec During data transfer, SDA line may only change while SCL line is low –SDA line change while SCL high has special meaning.

17. Lecture 1117 Starting and Stopping Transfers When bus idle, both SDA, SCLK are high Indicate start and stop of a bus transaction by transitions on SDA while SCLK high

18. Lecture 1118 Clock Period Determination Master starts by pulling clock line low –All devices see this, also pull the clock low, and wait for its required clock low period –The SCL line will be held LOW by the device with the longest LOW period. Devices with shorter LOW periods enter a HIGH wait-state during this time When all devices see clock go high, begin counting off (wait for) its clock high period and pull the SCL line low –SCL goes low when the first device reaches the end of its clock high period – SCL high period is determined by the shortest clock HIGH period

19. Lecture 1119 Arbitration Bus supports multiple masters, need way to decide which one wins if multiple try to drive at the same time Arbitration mechanism: all masters drive bus, when a master sees the SDA bus having a difference with its own value, it loses and gives up

20. Lecture 1120 Sending Data Byte-oriented interface requires an acknowledgement from receiver after each byte –Master generates clock pulse for this bit –Receiver pulls data line low to acknowledge –Master must abort transfer (with transfer stop) if any byte not acknowledged Devices have addresses (8-bit) that they use to determine whether they should pay attention to a bus transfer –Device address typically burned into the hardware –Can’t have two devices with the same address on a bus Some devices have one or more programmable address bits to get around this limitation Master sends transfer start, followed by address, followed by a variable number of data bytes. Ends transaction with transfer stop

21. Lecture 1121 Data Example

22. Lecture 1122 Using I 2 C to Program the ADV7183B ADV7183B has a large number of control registers –Select input format –Processing of input image, auto detection, etc. Most registers are read-write, some are read-only –As part of initialization, you may need to write all writeable registers, even those that are reserved –ADV7183B uses a “subaddress” to select these –Easiest way to do this is to build hardware that maps sequential writes to a PCMCIA memory location onto I 2 C bus transactions

23. Lecture 1123 Writing to ADV7183B Registers Address specifies ADV7183B, first data byte gives subaddress (register specifier), second byte is data to be written

24. Lecture 1124 Reading From ADV7183B Registers Uses “combined” format, where a master sends multiple transfers without a stop bit –First transfer specifies subaddress –Second moves data

25. Lecture 1125 ADV7183B Control Registers ADV7183B defines 256-byte control register space (00-FF) –Do this with software loop on the IPAQ – FPGA hardware should just translate PCMCIA  I 2 C –Note that some bytes are read-only (writes to them should be ignored by hardware)

26. Lecture 1126 Control Registers Several different types –Analog input type selection –Output type selection –Definition of sync signals –Luminance/chroma control (should be able to create special effects by adjusting these) –Status outputs –Outputs describing which line is being scanned Hint: –ADV7183B Video Decoder manual in the class web –Pages 62-66 define a set of values for the control registers that auto-detect NTSC input signals and give standard YUV outputs –Pages 88-89 give some programming examples

27. Lecture 1127 Next Time VGA Video