2. Agenda Last Year’s Mission The Road Ahead Summary

3. Last Year’s Mission Accomplished Feature Size (micron) 0 0.2 0.4 0.6 0.8 1 1.2 1990199219941996199820002002 5v 3.3v 2.5v 1.8v 1.3v 4Process Leadership 4Density Leadership 4Performance Leadership 4Price & Value Leadership 4Software Leadership

4. Transistor Count (millions) XC40125XV XC40150XV XC40250XV 0.25u Process Virtex 1 Million Gate 7.5 25 50 75 2Q984Q97 3Q98 4Q98 1Q98 Process Leadership “samples today”

5. Density Leadership XC4085XL XC40125XV 1997 1998 1999 2000 2002 Virtex Density (system gates) 10M Gates In 2002 Virtex II 10 Million System Gates in 2002! XC40250XV 10M 2M 1M 250k 180k 500k

6. 4 Distributed Dual Port RAM 4 I/O Registers 4 Internal Bussing 4 5V Tolerant I/O 4 3.3V and 5V PCI Features q 133 MHz Block Dual Port RAM q System I/O (LVTTL, SSTL, GTL) q Vector Based Interconnect q Phase Locked Loops q 66 MHz 64-Bit PCI 1998 1999 2000 2001 2002 q Reconfigurable Logic q On-Chip A/D-D/A q Embedded Functions q 1GHz Diff. Interface q Built-in Logic Analyzer Architecture Innovation Leadership

7. * 1/(Tsetup+Tclock-to-out) System Clock Rate* (MHz) 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 199519961997199819992000 2001 2002 4PC 100 SDRAM Compliant 4100 MHz DSP for Wireless Base Station 433 MHz PCI Performance Leadership Enabling high performance solutions first q2002 System Standards q233 MHz uP q300 MHz RAM I/F q133 MHz SDRAM I/F q155 MHz SONET q 66 MHz PCI

8. Quality & Reliability Leadership Worldclass Today & Tomorrow DescriptionIndustry StandardXilinx TodayXilinx Future AOQL*< 25 ppm< 3.4 ppm< 3.4 ppm Reliability< 100 FITs< 10 FITs< 10 FITs MoistureJEDEC Level 3JEDEC Level 3JEDEC Level 2 Resistance ISO CertificationSome9001 & 90029001 & 9002 QML CertificationNoYesYes Delivery by OFD**No95%> 95% * Average Outgoing Quality Level ** Original Factory Commit Date

9. Chip Scale Fine Pitch BGA Flip Chip Technology PLCC PGA PQFP HQFP BGA SBGA 1998 2000 2002 Packaging Leadership 1.0mm <0.8mm 1.27mm 100 300 500 700 1000 Pins

10. Density (System Gates) 199719981999200020012002 15K 40K 100K 100K unit volume price projections 60K New Applications Set Top Box DVD Digital Camera PC Peripherals Consumer Electronics New Applications Set Top Box DVD Digital Camera PC Peripherals Consumer Electronics 25K 60K 200K 100K 10K Gates/$ in 2002! Priced for High-Volume Leadership

11. 1998 1999 2000 2001 2002 Spartan $3 95 Spartan $3 95 Price SpartanXL $2 95 SpartanXL $2 95 0.35  5LM Spartan-II < $2 00 Spartan-II < $2 00 0.5  3LM 2.5 Volt More Features Without Compromises  Pricing competitive with ASICs  High Performance  On-chip SelectRAM TM  PCI LogiCORE + AllianceCORE 3.3 Volt 5 Volt *Prices are for 5K system gates, 100K units, -3 speed, Lowest Cost Package 0.25  5LM Spartan Next Generation < $1 50 Spartan Next Generation < $1 50 1.8 Volt 0.18  FPGA Price Leadership

12. Price XC9536/XL $0.80 $7 $1.80 $15 20012000199919982002 XC95216/XL Without Compromises Flexible ISP t PD = 4ns Best Pin-Locking Industry Standard JTAG * Prices are based on 100Ku+, slowest speed grade, lowest cost package CPLD Price Leadership

13. 1998 2000 2002 q Team Based Design q Modular Guide q Modular Compile q HDL- Centric Flows Software Leadership 4Largest Installed Base 4Highest Circuit Performance with M1 4Fastest Timing Driven Compile Times 4Shrink-Wrapped FPGA Express 4Best flows & QOR with leading EDA vendors 4Push Button Design

14. Release 1.5 is Hot  5 New FPGA/CPLD Families  2x Runtime Improvements  Graphical Constraints Editor  Floorplanner  Automatic Pin Locking  6x Faster Timing Analysis (Kpaths algorithm)  Automatic Clock Skew Handling  New Reporting of Minimum Delays  Voltage and Temperature Speed Pro-rating

15. Compile Time Leadership 1999 Goal: 1 Million Gates in 45 minutes! Faster CPUs Faster Compile Times Modular Compile 0 20 40 50 60 70 80 90 100 1.41.52.12.2 Minutes* * 100k System gate designs (200MHz Pentium) Release Up to 6X faster than 1.3 30 10 And with...

16. The Road Ahead Design Methodology Evolution Density (system gates) 25K 100K 500K Process Technology.5u.35u.25u

17. L Design From Scratch Reference Design, Generic Core D Verify V Learn V Complete FPGA Core Solution I Implement I L D Months Pre-verified Designs Area & Timing Optimized Complete & Flexible Design Little Knowledge of Function Required Complete Core Solutions Reduce Time To Market

18. Available Only From Xilinx High Flexibility High Predictability Intelligent Software Implementation Intelligent Software Implementation Architectures tailored to cores Flexible Core Technology High Performance Xilinx Smart-IP Technology Xilinx Smart-IP Delivers

19. Advantages Efficient Routing Predictable Timing Low Power Xilinx Segmented Routing Non-Segmented Routing Core1 Core2 Architecture Tailored to Cores RAM available locally to the Core Advantages Portable RAM based Cores Improved Logic Efficiency by 16X High Performance Cores Segmented Routing Distributed Memory

20. Enhances Performance & Predictability Intelligent Software Pre-defined Placement & Routing Relative Placement Other Logic Has No Effect on the Core Fixed Placement & Pre-defined Routing Guarantees Performance Guarantees I/O & Logic Predictability Fixed Placement I/Os

21. Data sheets CoreLINX: SystemLINX: Web Mechanism to Download New Cores Third Party System Tools Directly Linked With Core Generator Parameterized Cores Flexible Core Technology Optimal Core Creation & Flexible Core Delivery Free Software & Free Cores Included (Cores offer over a 1,000,000 Permutations!)

22. Performance Independent of a Core’s Placement or the number of cores used in the Device 80 MHZ Smart-IP Delivers Design Portability Performance Independent of Device Size Non-Segmented Architecture May Experience 30% Performance Degradation 80 MHZ

23. 1998 1999 Standard Bus Interfaces DSP Functions Communication & Networking Base Level Functions PCMCIA USB CAN Bus ISA PnP I2C PCI 32bit Add, Subtract, Integrate Correlators Filters: FIR, Comb Multipliers Transforms: FFT, DFT Sin/Cos ATM Cell Assembly/Delineation CRC-16/32 T1 Framer HDLC Reed-Solomon, Viterbi UTOPIA, 25/33/50 MHz 82xx, UARTs, DMA, 66 MHz DRAM/SDRAM I/F Memory (RAM, ROM, FIFO) Micro Sequencer (2901) Proprietary RISC Processors CardBus FireWire(100-400 Mbps) PCI 64bit/66MHz PC104 VME DCT Cordic DES Divider JPEG NCO 10/100 Ethernet 1Gb Ethernet ADSL, HDSL, XDSL ATM/IP Over SONET SONET OC3/12 Microprocessor I/Fs 8051/8031 IEEE 1284 MIPS 133+ MHz SDRAM I/F Emerging High- Speed Standard Interfaces DSP Processor I/Fs DSP Functions > 200 MSPS Programmable DSP Engines QAM Modems SONET OC48 Emerging Telecom and Networking Standards Satellite decoders Speech Recognition Advanced Processors 2000 By 2002: Virtually All Functions Available as Cores Leader in Core Solutions Xilinx and Partners’ COREs

24. Xilinx Applications on The Rise From Standard Products & Gate Arrays to Systems on a Programmable Chip

25. Simple & Fast Low Cost CPLD Solutions Isolates User From Interface Issues Critical Signal Timing Electrical Interfacing Control Signal Sequencing (State Machine Design) Variances In Interfaces SDRAM (i.e. Bank vs. SIMM) Unique System Back-End

26. Flexible High Density FPGA Solutions JPEG Compression (70k ASIC Gates + RAM) FPGA Advantages over Chipsets Can specify Non-Standard Data-Rate & Pixel Depth Industrial Temp Range High Performance 2x NTSC Video Resolution 1.5x NTSC Pixel Depth

27. Core Function XCS30XL Price Percentage of Device Used Effective Function Cost UART$6.95 17% $1.20 16-bit RISC Processor $6.95 36% $2.50 16-bit, 16-tap Symmetrical FIR Filter $6.95 27%$1.90 Reed-Solomon Encoder $6.95 6% $0.40 PCI Interface (w/ faster speed grade) $12.0045% $5.40 High Value Applications with Spartan

28. External PLD 15K Gates Component Cost 100K Units Standard Chip PCI Master I/F $5 $15 $20 $10 Costs less Than Standard ICs! Standard Chip Solution >$20 PCI Master I/F User Design 15K Gates Xilinx PCI Solution <$13.50

29. 1.6 1.2 0.8 0.4 Giga-MACs * Prices based on 50k volume $192*$9.95* 2 Extra uPs1 Extra uP3 Extra uPs Delivers High Performance At a Fraction Of The Cost Integrated System Level Tools Easy Parameterization Tools Free Parameterization

30. The Road Ahead Design Methodology Evolution 500K.25u.18u Density (system gates) Process Technology 1 Million

31. Designer1 Module Design Reuse Designer2 Module Designer3 Module Reduces Compile Time & Increases Performance Xilinx Enables Modular Design  Facilitates Group Design & Reuse  Seamless Integration Between Modules Extension to leading cores solution  Modular Time Specs With industry’s best timing constraint language  Modular Incremental Compile Extensive R&D investment

32. Fast I/O Performance 4Phase Lock Loops 4155MHz SONET 4133MHz SDRAM 466MHz PCI Flexible, Fast RAM 4133MHz External, Block, and Distributed RAM 4Fully Dual Ported (2 independent read/write ports) 4Configurable Data Widths and Depths 4SSTL3 Interface to External RAM Virtex The Ideal Platform for Modular Design Predictably Fast Performance 4Vector Based Interconnect 410ns Global Signals 4100MHz+ from all devices Flexible Interfaces 4LVTTL, LVCMOS 4SSTL, GTL, PCI 9Future Standards

33. Virtex Enables System on a Programmable Chip VHDL Design Environment Verilog Design Environment CoreGen Designer #2 DSP Designer #1 New Modules FIFO 133Mhz SDRAM Gbit Ethernet 66Mhz PCI IP Modules LogiCore AllianceCore CPU Design Reuse 160 MHz I/O Performance 133 MHz Memory Performance 1 Million System Gates

34. Functional FPGA Equivalence Support for Complex FPGA Cores Risk and Resource Reduction No Re-engineering from FPGA CLB Integrity Maintained Planned for 2H 2000 Introduction FPGA HardWire FpgASIC HardWire FpgASIC’s The only ASIC solution designed for Virtex Gbit Ethernet 133Mhz SDRAM Logic SDRAM

35. $0 $50 $100 $150 $200 $250 $300 400K Gates 600K Gates 800K Gates 1 Million Gates 2001 2002 HardWire FpgASIC 100K unitsVirtex FPGA 50K units Virtex + FpgASIC Cost Effective System on a Chip

36. The Road Ahead Design Methodology Evolution 1 Million 10 Million.15u.18u

37. System Gates Total Development Time 10k 100k 1M 10M 100M Integration Time Design Time Increased Integration Time Requires Team Based Design

38. Xilinx To Deliver Team Based Design Solutions Team Oriented Design Mgmt Engineering Change Control Team Oriented Design Mgmt Engineering Change Control Module Timing Independence Fixed Timing On a Module Module Timing Independence Fixed Timing On a Module Timing Budget Calculator Module Based Timing Redistribution Timing Budget Calculator Module Based Timing Redistribution Global Timing Defn & Optimization Auto Inter-Team Floorplanning

39. Real Technology Partnerships Xilinx Delivers  Committed to Product Leadership  Focused on Complete Solutions  Driving New Applications With Cores  Delivering the Vision