1. Victor Zhirnov July 10, 2011 San Francisco, CA
ERD Memory Discussion
Victor Zhirnov
July 10, 2011
San Francisco, CA

2. Outline ERD Memory Tables/Text Updates Memory Select Device Section
Storage Class Memory Section

3. ERD Memory Tables

4. 2011 Memory Transition Table
IN/OUT (Table ERD5)
Reason for IN/OUT
Comment
Emerging Ferroelectric Memory IN
Replaces former FeFET category and the ferroelectric polarization/electronc effects memory categories
Redox memory
Replaces former nanothermal and Ionic memory categories
Mott Memory
Separated from the electronic effects memory
FeFET Memory
OUT
Merged with FeFET and the ferroelectric polarization/electronc effects memory
Electronic effects memory
Replaced by EFM and Mott
Nanothermal memory
Merged with Ionic Memory to form Redox Memory Category
Nanoionic memory
Merged with Nanothermal Memory to form Redox Memory Category
Spin Torque Transfer MRAM
Became a prototypical technology
Spin Torque Tranfer MRAM is already included in PIDS chapter since 2009 (Tables PIDS5 and PIDS 5A)

5. 2011 ERD Memory Table Emerging Ferroelectric memory
Emerging Ferroelectric memory
Nanomechanical Memory
Redox Memory
Mott Memory
Macromolecular Memory
Molecular Memories
Storage Mechanism
Remnant polarization on a ferroelectric gate dielectric
Electrostatically-controlled mechanical switch
Ion transport and
Multiple mechanisms
redox reaction
Cell Elements
1T or 1T1R
1T1R or 1D1R
Device Types
FET with FE gate insulator
FTJ
1) nanobridge
1) cation migration
M-I-M (nc)-I-M
Bi-stable switch
2) telescoping CNT
2) anion migration
Mott transition
3) Nanoparticle

6. Emerging Ferroelectric Memory
Combines two subcategories:
Ferroelectric FET
Ferroelectric tunnel junction
Should not be confused with conventional ferroelectric memory or FeRAM
Based on FE capacitor
Is currently in PIDS
Temporary working name:
Emerging Ferroelectric Memory
Suggestions are welcome

7. Emerging Ferroelectric Memory
Text update: completed
Table ERD5 update: Work in progress
References update: Work in progress

8. Nanomechanical Memory
Text update: completed
De-emphasized CNT-based nanomechanical memory (earlier Nantero concept)
Table ERD5 update: Work in progress
References update: Work in progress

9. RedOx Memory References update: Work in progress
Replaces former nanothermal and Ionic memory categories
New text based on the materials from Barsa Workshop (white papers and presentations)
Numbers in Table ERD5 updated
References update: Work in progress

10. Macromolecular Memory
Text update: Work in progress
Table ERD5 update: Work in progress
References update: Work in progress

11. Molecular Memory References update: Work in progress
Text update: Work in progress
Table ERD5 update: Work in progress
References update: Work in progress

12. Input Received Alex Bratkovski (HP) Curt Richter (NIST)
Eric Pop (U Illinois)
An Chen (GLOBALFOUNDRIES)
Rainer Waser (U Aachen)
Hiro Akinaga (AIST)
Table ERD5/Redox Memory
Table ERD5/Redox Memory
Table ERD4/PCM
Table ERD5/Mott Memory
Text / References
Text / References

13. Memory Select Device Wei Lu (U Michigan) An Chen (GLOBALFND)
Dirk Wouters (IMEC)
Kwok Ng (SRC) Victor Zhirnov (SRC)

14. Memory Select Device TWG:
Wei Lu (U Michigan) An Chen (GLOBALFND)
Dirk Wouters (IMEC)
Kwok Ng (SRC) Victor Zhirnov (SRC)
The fundamental study team
Rainer Waser (U Aachen) Thomas Vogelsang (RAMBUS) Zoran Krivokapic(GLOBALFND) Al Fazio (Intel)
Kyu Min (Intel)
U-In Chung (Samsung)
Matthew Marinella (Sandia Labs)

15. Memory Select Device: Intro
A memory cell in array can be viewed as being composed of two fundamental components: the ‘Storage node’, and the ‘Select device’ to minimize sneak current through unselected cells.
Both components impact scaling limits for memory.
Several advanced concepts of resistance-based memories offer storage node scaling down below 10 nm, and the memory density will be limited by the select device.
The select device thus represents a serious bottleneck for memory scaling to 10 nm and beyond.

16. Suggested select device categories
Select devices
Transistor
Planar
Vertical
Diode
p-n junction
Schottky junction
Hetero-junction
Switch-based selector
Mott transition switch
Threshold switch
Resistive switch
Mixed ionic electronic conduction (MIEC)
Complementary resistive switch structure
Placement of Rainer’s device in the table?

17. Planar FET select device
L. Li, K. Lu, B. Rajendran, T. D. Happ, H-L. Lung, C. Lam, and M. Chan, “Driving Device Comparison for Phase-Change Memory”, IEEE Trans. Electron. Dev. 58 (2011)

18. Vertical Select Devices
Vertical diode
Vertical FET
L. Li, K. Lu, B. Rajendran, T. D. Happ, H-L. Lung, C. Lam, and M. Chan, “Driving Device Comparison for Phase-Change Memory”, IEEE Trans. Electron. Dev. 58 (2011)

19. Vertical Select Devices
Vertical diode
4F2
Vertical FET
5.3F2

20. Vertical Transistor Select Devices
Experimental demonstrations of vertical transistors in memory arrays.
Technology
Memory Type
Array size
Cell size
Transistor
Ion
Von
Ion/Ioff
Infineon (2004)1
170 nm
DRAM
1 Mb
8F2
DG FET
50mA
1.8V
1010
Samsung (2010)2
80 nm
50 Mb
4F2
GAA FET
30mA
1.2V
1011
Hynix&Innovative Silicon (2010)3
54 nm
Z-RAM -
0.5V
Numonix (2009)4
45 nm
PCM
1Gb
5.5F2
BJT
300mA 2V
NTHY&ITRI
(2010)4
180 nm
ReRAM
4F2*
100mA
A*STAR (2008)5 **
25 nm
(NW dia)
NWGAA FET
25mA
107
* projected cell size
**has potential as a select device (not demonstrated)

21. Two-terminal selector devices
External 2-terminal structure with non-linear characteristics
e.g. switching diode-type behavior for unipolar memory cells
for bipolar cells, selectors with two-way switching behavior are needed, e.g. Zener diode, avalanche diode etc.
Storage element with inherent rectifying/isolation properties I V
ION1
ON2
ION
OFF
ON1
OFF
unipolar
bipolar

22. Benchmark Select Device Parameters
Value
Driver
ON Voltage, Vr
~1 V
Compatibility with logic; low-power operation
ON current, Ir
~10-6 A
Sensing of memory state (fast read)
ON/OFF ratio*
>106
Sufficiently low ‘sneak’ currents **
Operating temperature
85°C
50°C
The top end spec for servers. 
NAND spec (the very embodiment of non- volatile memory for the current state-of-the-art),
*ON/OFF current ratio at ~(1V) supply
**Proposed alternative schemes of array biasing could result in relaxed requirements on the select device ON/OFF ratio [5]

23. Diode-type Select Devices
pn-diode,
Schottky diode
Heterojunction diode
BARITT diode
Zener diode
Reverse breakdown Schottky diode
Unipolar cell
Bipolar cell

24. Reverse breakdown Schottky diode
Diode-type Select Devices
Selector type
Material System
Von1
Ion1
Von2
Ion2
ON/OFF F
REF
Unipolar cell
pn-diode
Poly-Si (E) 1
20 mA
2×104 A/cm2 -
105
0.3 mm
van Duuren 2007
Schottky diode
n-ZnO (E)
45 mA
500 A/cm2
3 mm
Huby 2008
Ge NW (E)
1 mA
102
0.5 mm
Wong 2008
a-Si (I)
100 nA
1000 A/cm2
106
100 nm
Lu 2010
p-Si (E)
10 mA
103
1 mm
Lee 2010
Pt/TiO2
6 mA
10 A/cm2
109
245 mm
Hwang 2010
Heterojunction diode
n-ZnO/p-Si 3
25 mA
250 A/cm2
100mm
Choi 2010
CuO/InZnO
2.5 mA
Park 2009
Bipolar cell
Zener diode
(E)
Toda 2009
Reverse breakdown Schottky diode
Cu/n-Si -3
2 mm
Kozicky 2010

25. Switch-type select devices
Innovative device concepts that exhibit resistive switching behavior.
In some of these concepts the device structure/physics of operation is similar to the structure of the storage node.
A modified memory element could act as select device!
a ‘nonvolatile’ switch is required for the storage node, while for select device depending on the approaches non-volatility may not be necessary and can sometimes be detrimental.
Knowledge gained from studying new memory phenomena can be used for select device!

26. Resistive-Switch-type select devices I
Mott-transition switch
is based on the Mott Metal-Insulator transition
a volatile resistive switch,
A VO2-based Mott-transition device has been demonstrated as a selection device for NiOx RRAM element [Ref: M.J. Lee, “Two Series Oxide Resistors Applicable to High Speed and High Density Nonvolatile Memory,” Adv. Mater. 19, 3919 (2007).].
The feasibility of the Mott-transition switch as selection devices still needs further research.
Threshold switch
is based the threshold switching in MIM structures caused by electronic charge injection/trapping
Significant resistance reduction can occur at a threshold voltage and this low-resistance state quickly recovers to the original high-resistance state when the applied voltage falls below a holding voltage.

27. Resistive-Switch-type select devices II
MIEC switch
observed in materials that conduct both ions and electronic charges – so called mixed ionic electronic conduction materials (MIEC).
The resistive switching mechanism is similar to the ionic memories.
Complementary resistive switch
the memory cell is composed of two identical non-volatile ReRAM switches connected back-to-back.
Example: Pt/GeSe/Cu/GeSe/Pt structure
During idle conditions one of the ReRAM switch is off so sneak current is reduced.
Read involves turning on both ReRAM devices and is destructive.

28. Mott-Switch as Select Device
Combined device switching
Threshold Switching
Resistive Switching
Lee 2007
- demonstrated very fast writing and erasing process, 1.5V; 10ns.
- read operation at 0.6V also doesn’t seem to be degraded by switch element
- on/off ratio ~ 103, Ion ~ 400 A/cm2

29. Threshold switch as Select Device
Current
Voltage
Voltage
Current
Vread
VSet
VReset
Schematic I-V characteristics of threshold switch
Schematic I-V characteristics of combined unipolar RRAM devices with threshold switch as the select device
-Similar to Mott switch, but not restricted by the transition temperature
- Organic Threshold Switch as select device integrated with PCM (Kau 2009)
- 9ns switching speed and 106 endurance demonstrated
- Array data not available. Arrays based on MOS select devices presented

30. MIEC-Switch as Select Device
Switch device characteristics
Gopalakrishnan 2010
- MIEC switching due to redistribution of Cu ions and associated hole diff. current
- Current scales with BEC area. Needs very thin (~ 13nm) dielectric for high current
- Combined MIEC/PCM device demonstrated with endurance of > 3x104 cycles.

31. Complementary ReRAM cell
Two identical RRAM devices connected back-to-back
(1,1)
C-ReRAM 0 = (0,1)
C-ReRAM 1 = (1,0)
Waser 2010
(1,0)
(1,0)
(0,1)
(0,1)
VT,set<Vread<2VT,reset
Vc,reset
(1,1)
(1,0) -> (1,1), -> high read current
(0,1) -> (0,1), -> low read current
Vc,set
Vread

32. Complementary ReRAM cell
CRRAM cell
C-ReRAM based on back-to-back Pt/ZrOx/HfOx/BE devices
Read endurance is limited to 105
Lee 2010

33. Chalcogenide alloy (undisclosed)
Resistive-Switch-type select devices
Source: Philip Wong / Stanford
Select Device
Material System
Von1
Ion1
(Jon1)
ON/OFF F
REF
Mott transition switch
Pt/VO2/Pt
0.4/0.6V
(400 A/cm2)
103
Lee 2007
Threshold switch
Chalcogenide alloy (undisclosed)
106
Kau 2009
MIEC switch ~1
40 nm
Gopalakrishnan
2010
Complementary resistive switch
Pt/GeSe/Cu/GeSe/Pt 1
600 A
2400 A/cm2
5 mm
Waser 2010

34. Criteria for the evaluation of selection devices
Parameters
Explanations
Blocking state resistance
Measure the resistance from the selection devices in the blocking state; it is generally a voltage-dependent value
The higher the blocking state resistance the better
Conductive state resistance
Measure the resistance from the selection devices in the conductive state; it is generally a voltage-dependent value
The smaller the conductive state resistance the better
Turn-on voltage
The voltage where the selection devices become sufficiently conductive
Turn-on speed
How fast the selection devices turn on, which affect switching dynamics
Turn-off voltage
The voltage where the selection devices become nonconductive (high resistance)
Turn-off speed
How fast the selection devices turn off, which affect switching dynamics
Operation polarity
Blocking/conductive states exist in both polarities (suitable for bipolar switching devices) or each in different polarity (suitable for unipolar switching devices)
Scalability
How scalable is the selection devices
Linearity
Linear or nonlinear I-V characteristics in blocking and conductive states
Processing temperature
Low processing temperature is preferred
Materials
What materials are required? How available are they? Are they compatible with the processing of the resistive switching devices?
Structures
Two terminal or three terminal

35. Fundamental Issues
For scaled diode-type select devices two fundamental challenges are:
Contact resistance
Lateral depletion effects
Very high concentration of dopants are needed to minimize both effects.
high dopant concentrations result in increase reverse currents in classical diode structures and therefore in reduced ON/OFF ratio.
For switch-type select devices the main challenges are:
identifying the right material
and the switching mechanism to achieve the required drive current density, ON/OFF ratio and reliability.

36. Selection Devices Summary
Experimental two-terminal select devices have yet to meet the benchmark specifications
Hence, outstanding research issues persist
2011 MSD tables and text reflects both target parameters and experimental status
More detailed benchmarking and further analysis is currently underway
Currently no data from functional arrays based on two-terminal select devices are available

37. Solid-State Storage Class Memory

38. SCM Team:
Barry Schechtman (INSIC) Rod Bowman (Seagate) Geoff Burr (IBM) Bob Fontana (IBM) Michele Franceschini (IBM)
Rich Freitas (IBM) Kevin Gomez (Seagate) Mark Kryder (CMU) Antoine Khroueir (Seagate) Kroum Stoev (Western Digital) Winfried Wilcke (IBM)
Thomas Vogelsang (RAMBUS)
Matthew Marinella (Sandia Labs) Jim Hutchby (SRC) Victor Zhirnov (SRC)

39. Storage-class memory (SCM)
Research and development efforts are underway worldwide on several nonvolatile memory technologies that not only complement the existing memory but also reduce the distinction between memory and storage1
Memory: fast, evanescent, random-access, expensive
Storage: slow, permanent, sequential-access, inexpensive
Storage-class memory (SCM): Emerging solid-state technologies with (some) attributes of both memory and storage devices
May eventually replace discs and (perhaps) DRAM1
1 “Storage-class memory: The next storage system technology”, by R. F. Freitas and W. W. Wilcke, IBM J. Res. & Dev. 52 (2008) 439

40. Draft Section on SCM is Completed
Storage-class memory (SCM) describes a device category that combines the benefits of solid-state memory, such as high performance and robustness, with the archival capabilities and low cost of conventional hard-disk magnetic storage.
Such a device requires a nonvolatile memory technology that could be manufactured at a very low cost per bit.
As the scalability of flash is approaching its limit, emerging technologies for non-volatile memories need to be investigated for a potential “take over” of the scaling roadmap for flash.
In principle, such new SCM technology could engender two entirely new and distinct levels within the memory and storage hierarchy, located below off-chip DRAM and above mechanical storage, and differentiated from each other by access time.

41. Hard-disk Drive
Conventionally, magnetic hard-disk drives are used for nonvolatile data storage.
The cost of HDD storage (in $/GB) is extremely low and continues to decrease.
Issues:
poor random access time
relatively high energy consumption,
large form factor,
limited reliability.

42. Flash memory: Device Challenges
NAND flash has recently become an alternative storage technology
faster access times,
smaller size and potentially lower energy consumption, as compared to HDD.
The NAND-based solid state drive (SSD) market has flourished recently.
There are several serious limitations of NAND flash for storage applications
poor endurance (104 – 105 erase cycles),
modest retention (typically 10 years on the new device, but only 1 year at the end of rated endurance lifetime),
long erase time (~ms), and high operation voltage (~15V).

43. Flash SSD: Architectural Challenges
Page/block-based architecture,
doesn’t allow for a direct overwrite of data,
requiring sophisticated garbage collection
bulk erase procedures,
Computation-intensive data management
Takes extra memory space,
Limits performance
Accelerates the wearing out of memory cells.
Lower power potential compromised in current SSD implementations

44. Flash Scaling Challenges
Flash memory scaling doesn’t improve (and sometimes degrades) the basic performance characteristics
read, write and erase latencies have been nearly constant for over a decade
Extreme scaling results in the degradation of retention time and endurance,
critical for storage applications!
There are opportunities for prototypical and emerging memory technologies to enter the non-volatile solid state memory space.

45. Prototypical and emerging memory technologies for SCM applications
As the scalability of flash is approaching its limit, emerging technologies for non-volatile memories need to be investigated for a potential “take over” of the scaling roadmap for flash.
It appears that storage applications could be the primary driver for the new memory technologies,
may help to overcome the fundamental shortcomings of flash technology.
In principle, such new SCM technology could engender two entirely new and distinct levels within the memory and storage hierarchy, located below off-chip DRAM and above mechanical storage, which are differentiated from each other by access time.

46. I. S-type storage-class memory
The first new level, identified as S-type storage-class memory (S-SCM), would serve as a high-performance solid-state drive
accessed by the system I/O controller much like an HDD.
S-SCM would need to provide at least the same data retention as flash,
offering new direct overwrite and random access capabilities (which can lead to improved performance and simpler systems)
However, it would be absolutely critical that the device cost for S-SCM be no more than 1.5-2x(1-1.5x? IN THE MATURE STATE)) higher than NAND flash
If the cost per bit could be driven low enough through ultrahigh memory density, ultimately such an S-SCM device could potentially replace magnetic hard-disk drives in enterprise storage server systems.

47. II. M-type storage-class memory
M-SCM:
should offer a read/write latency of less than 1 ms.
would allow it to remain synchronous with a memory system, allowing direct connection from a memory controller and bypassing the inefficiencies of access through the I/O controller.
Would be to augment a small amount of DRAM to provide the same overall system performance as a DRAM-only system, while providing
Moderate retention,
Lower power-per-GB and lower cost-per-GB than DRAM.
Endurance is particularly critical
the time available for wear-leveling, error-correction, and other similar techniques is limited
> 109 cycles

48. Target device and system specifications for SCM
Parameter
Benchmark
Target
HDD*
NAND flash**
DRAM
Memory-type SCM
Storage-type SCM
Read/Write latency
3-5 ms
~100ms
(block erase ~1 ms)
<10 ns
<0.3ms
1-10ms
Endurance (cycles)
unlimited
105
>109
108
Retention
>10 years
~10 years
64 ms
>5 days
ON power (W/GB)
~0.04 ~
0.4
Lower (per GB) than DRAM
Lower (per GB) than HDD
Standby power
~20% ON power
<10% ON power
~25% ON power
<1% ON power
Areal density
~ 1011 bit/cm2
~ 1010 bit/cm2
~ 109 bit/cm2
>109 bit/cm2
Cost ($/GB)
0.1 2 10
Lower than DRAM
Within (1.5-2x?) of NAND Flash
* enterprise class
**single-level cell (SLC)

49. Prototypical and emerging memory technologies for SCM applications
Necessary attributes of a memory device for the storage-class memory applications are:
Scalability
Multilevel Cell - MLC (MLC vs extreme scaling dilemma)
3D integration (stacking)
Fabrications costs
Endurance (for M-SCM)
Retention (for S-SCM)
The driving issue is to minimize the cost per bit

50. Potential of the current prototypical research memory candidates for SCM applications
Parameter
FeRAM
STT-MRAM
PCRAM
Scalability
low
medium
good
MLC no
difficult
yes
3D integration
Fabrication cost
Endurance
excellent
average
A likely introduction of these new memory devices to the market is by the hybrid solid-state discs, where the new memory technology complements the traditional flash memory to boost the SSD performance.
Experimental implementations of FeRAM/flash and PCRAM/flash have recently been explored. It was shown that the PCRAM/Flash hybrid improves SSD operations by decreasing the energy consumption and increasing the lifetime of flash memory.

51. Potential of the current emerging research memory candidates for SCM applications
Parameter
Ferroelectric memory
Nanomechanical memory
Redox memory
Mott Memory
Macromolecular memory
Molecular Memory
Scalability
MLC
3D integration
Fabrication cost
Endurance

52. “Traffic Light” indicators
                Green:  this entry has good progress; there are no or few issues.
          Yellow:  this entry’s potential is not clear; there is a number of issues.
           Red: this entry’s potential is questionable; there is a list of issues.
Message might be softer, a bit more proactively positive (or at least hopeful).

53. Proposal from Toshiba

54. Table 1 (current version)
Parameter
Benchmark
Target
HDD*
NAND flash**
DRAM
Memory-type SCM
Storage-type SCM
Read/Write latency
3-5 ms
~100ms
(block erase ~1 ms)
<10 ns
<0.3ms
1-10ms
Endurance (cycles)
unlimited
105
>109
108
Retention
>10 years
~10 years
64 ms
>5 days
ON power (W/GB)
~0.04 ~
0.4
Lower (per GB) than DRAM
Lower (per GB) than HDD
Standby power
~20% ON power
<10% ON power
~25% ON power
<1% ON power
Areal density
~ 1011 bit/cm2
~ 1010 bit/cm2
~ 109 bit/cm2
>109 bit/cm2
>1010 bit/cm2
Cost ($/GB)
0.1 2 10
Lower than DRAM
Within (1.5-2x?) of NAND Flash
* enterprise class
**single-level cell (SLC)

55. Table 1 (proposed)
<10 ns
>106
~109 bit/cm2

56. Other proposals
How about to mention about emerging NVM technologies? Such as FusionIO, NVM express, and so on.
How about to merge Table 2 and 3?

57. Architectural Implications
Advances in SCM could drive the emerging data-centric chip architectures
Nanostores
Nanostores architectures could be an important direction for the future of information processing.
Addressed in the ERA section
Computer, Jan. 2011

58. Input Received Atsuhiro Kinoshita (Toshiba) Dirk Wouters (IMEC)
Rainer Waser (U Aachen) Thomas Vogelsang (RAMBUS) Matthew Marinella (Sandia Labs)
Geoff Burr (IBM) Bob Fontana (IBM) Kevin Gomez (Seagate) Mark Kryder (CMU)
Paul Frank (INSIC)