Presentation on theme: "Emerging Research Memory Devices: Status and 2012 plans"— Presentation transcript:
1Emerging Research Memory Devices: Status and 2012 plans International ERD TWG Emerging Research Devices Working Group Face-to-Face MeetingEmerging Research Memory Devices: Status and 2012 plansVictor Zhirnov / SRCWashington, DC, December 4, 2011
2Memory Team: An Chen (GLOBALFND) Zoran Krivokapic(GLOBALFND)Al Fazio (Intel)Atsuhiro Kinoshita (Toshiba)U-In Chung (Samsung)Rich Liu (Macronix)Hiro Akinaga (AIST)Wei Lu (U Michigan) Dirk Wouters (IMEC)Kwok Ng (SRC) Thomas Vogelsang (RAMBUS)Matthew Marinella (Sandia Labs) Rainer Waser (Aachen U) Victor Zhirnov (SRC)Barry Schechtman (INSIC) Rod Bowman (Seagate) Geoff Burr (IBM) Bob Fontana (IBM) Michele Franceschini (IBM)Rich Freitas (IBM) Kevin Gomez (Seagate) Mark Kryder (CMU) Antoine Khroueir (Seagate) Kroum Stoev (Western Digital) Winfried Wilcke (IBM)
3Input Received Alex Bratkovski (HP) Curt Richter (NIST) Eric Pop (U Illinois)Table ERD5/Redox MemoryTable ERD5/Redox MemoryTable ERD4/PCM
4Outline 2009-2011 Fundamental Studies Review 2011 ERD memory tables and textDiscussion on Specific Emerging Memory DevicesDiscussion of Memory Select DevicesDiscussion of Storage Class MemoryPlans for 2012
52010-11 Important Events Emerging Research Memory Devices Workshop Barza, Italy, April 2, 2008Emerging Memory Materials workshop Tsukuba, Japan, November 30, 2010ERD Face-to-Face meeting Potsdam, Germany, April 10, 2011San Francisco, USA, July 10, 2006
6ERD Memory Group Fundamental Studies in 2009-2011
72009 Challenge Lack of quantitative data For many memory entries, there were no referenced scaling projectionsOptimistic expectations/claims were used to fill the ERD memory tablesThe ERD Memory Group decided to develop reference documents containingBrief theory of operation with scaling limits projectionsReferences to the state-of-the artERD Memory activity focused on the development of quantitative data to support assessments of different memory entriesTo be continued in
8ERD Memory Group Publishing Activity Electronic Effects MemoryRedOx (Ionic) MemoryMemory Select DeviceH. Schroeder, V. V. Zhirnov, R. K. Cavin, R. Waser, Voltage-time dilemma of pure electronic mechanisms in resistive switching memory cells", JOURNAL OF APPLIED PHYSICS 107 (2010)Charge trapping induced resistive switching is not considered in 2011 ERD chapter, as a scaling of this memory technology below 100 nm is difficulty for any conceivable material combinationV. V. Zhirnov, R. K. Cavin, S. Menzel, E. Linn, S. Schmelzer, D. Bräuhaus, C. Schindler and R. Waser, “Memory Devices: Energy-Space-Time Trade-offs”, Proc. IEEE 98 (Dec. 2010) 2185V. V. Zhirnov, R. Meade, R. K. Cavin, S. Menzel, and G. Sandhu, “Scaling Limits of Resistive Memories”, Nanotechnology 22 (June 2011)Scaling and performance projections for <10nm ReRAMWei Lu1, An Chen2, Kwok Ng3 and Victor V. Zhirnov3, “Select Devices for Extremely Scaled Memory Arrays”, in preparation1University of Michigan ; 2GLOBALFOUNDRIES; 3Semicondcutor Research Corp.
102011 Memory Transition Table IN/OUT (Table ERD5)Reason for IN/OUTCommentEmerging Ferroelectric MemoryINReplaces former FeFET category and the ferroelectric polarization/ electronic effects memory categoriesFerroelectric polarization/ electronic effects memory has same difficult problems as FeFET, e.g. scalability, retention, endurance fatigueRedox memoryReplaces former nanothermal and Ionic memory categories Former ‘Nanothermal’ and ‘Nanoinic’ entries often referred to related mechanisms of resistive switchingMott MemorySeparated from the electronic effects memoryFeFET MemoryOUTMerged with FeFET and the ferroelectric polarization/electronc effects memoryElectronic effects memoryReplaced by EFM and MottNanothermal memoryMerged with Ionic Memory to form Redox Memory CategoryNanoionic memoryMerged with Nanothermal Memory to form Redox Memory Category Related mechanism to Nanothermal memorySpin Torque Transfer MRAMBecame a prototypical technologySpin Torque Tranfer MRAM is already included in PIDS chapter since 2009 (Tables PIDS5 and PIDS 5A)
112011 ERD Memory Table Emerging Ferroelectric memory Emerging Ferroelectric memoryNanomechanical MemoryRedox MemoryMott MemoryMacromolecular MemoryMolecular MemoriesStorage MechanismRemnant polarization on a ferroelectric gate dielectricElectrostatically-controlled mechanical switchIon transport andMultiple mechanismsredox reactionCell Elements1T or 1T1R1T1R or 1D1RDevice TypesFET with FE gate insulatorFTJ1) nanobridge1) cation migrationM-I-M (nc)-I-MBi-stable switch2) telescoping CNT2) anion migrationMott transition3) Nanoparticle
12Emerging Ferroelectric Memory In 2011 ERD combines two subcategories:Ferroelectric FETFerroelectric tunnel junction (FTJ)Motivation for mergingOperation principle of FTJ is based on ferroelectric polarization, similar to FeFETSame difficult problems as in FeFETRetention, endurance fatigue, scalabilityThis merging did not work well: The physics of READ and WRITE are very different for FeFET and FTJ memoriesDifficult to display the performance data in one columnProposal: To split FeFET and FTJ in two separate entries in 2013
13Ferroelectric FET & memory Number of publications(94+23)FeFETFTJ
14Nanomechanical Memory (NEMM) Difficult ChallengesScalabilityW. Y. Choi, T. Osabe and T-S. K. Liu, “Nano-electro-mechanical nonvolatile memory (NEMory) cell design and scaling”, IEEE Trans. Electron Dev. 55 (2008)Reliability/Endurancetypically fail after ~100 switching cycles[B4] J-W. Han, J-H. Ahn, Y-K. Choi, "FinFACT - fin flip-flop actuated channel transistor", IEEE Electron Dev. Lett. 31 (2010) 764J. Andazane et al., “Two-terminal nanoelectromechanical devices based on germanium nanowires”, Nano Lett. 9 (2009) 1824K. Lee and W. Y. Choi, “Nanoelectromechanical Memory Cell (T Cell) for Low-Cost Embedded Nonvolatile Memory Applications”, IEEE Trans. Electron Dev. 58 (2011)O. Loh; X. Wei; C .Ke; et al. “Robust Carbon-Nanotube-Based Nano-electromechanical Devices: Understanding and Eliminating Prevalent Failure Modes Using Alternative Electrode Materials”, SMALL 7 (2011) 79-86Y. Choi and T-J. K. Liu, “Reliability of nanoelectromechanical nonvolatile memory (NEMory) cells”, IEEE Electron Dev. Lett. 30 (2009)Best projected>50 nm [B1, B2]Demonstrated500 nm [B3, B4]Low voltage (~ 1V) operationDemonstrated~1E3 [B4]Should NEMM be in ERD in 2013?
15Nanomechanical Memory (NEMM) Number of publications
16RedOx MemoryFormer ‘Nanothermal’ and ‘Nanoinic’ entries often referred to related mechanisms of resistive switchingRecent experimental demonstrations of scalability, retention and endurance are encouragingMany details of the mechanism of the reported phenomena are still unknownNumber of publications(+30+44)(+99+77)
17Mott Memory A new entry in 2011 More research on the size effect of the Mott transition properties is needed to address the fundamental scaling limit of this type of devices.What is the minimum number of atoms in a Mott memory element to provide retention and sensing properties?Needs to be investigated under benchmark values
18Mott memory recent publications D. Ruzmetov, G. Gopalakrishnan, J. Deng, V. Narayanamurti, S. Ramanathan, “Electrical triggering of metal-insulator transition in nanoscale vanadium oxide junctions”, J. Appl. Phys. 106 (2009)S. D. Ha, G. H. Aydogdu, and S. Ramanathan, “Metal-insulator transition and electrically driven memristive characteristics of SmNiO3 thin films”, Appl. Phys Lett. 98 (2011)K-H. Xue, C. A. Paz de Araujo, J. Celinska, C. McWilliams, “A non-filamentary model for unipolar switching transition metal oxide resistance random acess memories”, J. Appl. Phys. 109 (2011)J. Celinska, C. McWilliams, C. Paz de Araujo, K-H. Xue, “Material and process optimization of correlated electron random access memories”, J. Appl. Phys. 109 (2011)C. R. McWilliams, J. Celinska, C. A. Paz de Araujo, K-H. Xue, “Device characterization of correlated electron random access memories”, J. Appl. Phys.109 (2011)L. Cario, C. Vaju, B. Corraze, V. Guiot, E. Janod, “Electric-field-induced resistive switching in a family of Mott Insulators: Toward a new class of RRAM memories”, Adv. Mat. 22 (2010)M. K. Niranjan, Y. Wang, S. S. Jaswal, and E. Y. Tsymbal, “Prediction of a switchable two-dimensional electron gas at ferroelectric oxide interfaces’, Phys. Rev. Lett. 103 (2009)20 publications in
19Macromolecular Memory Also referred to as polymer or organic resistive memoryConsists of a film of organic material sandwiched between two metal electrodesThe organic film is typically relatively thick (~many monolayers)Reduced fabrication cost is often considered as the primary driver for this type of memoryExtreme scaling is de-emphasizedMechanism of operation is not clearThere are some indications on the RedOx effectsPossible transition to the RedOx Memory category?
21Molecular MemoryA broad term encompassing different proposals for using individual molecules or small clusters of molecules as building blocks of memory cells.The concept emphasizes extreme scalingin principle, one bit of information can be stored in the space of a single moleculeThe success of molecular electronics depends on our understanding of the phenomena accompanying molecular switching,currently many questions remain unansweredMolecular memory is viewed as a long term research goal
22Molecular Memory Number of publications 2001-2003 43 2003-2005 68
23ERD Memory: Research Activity RedOxMacromolecularMolecularFeFETNEMM
25Memory Select Device: Intro A memory cell in array can be viewed as being composed of two fundamental components: the ‘Storage node’, and the ‘Select device’ to minimize sneak current through unselected cells.Both components impact scaling limits for memory.Several advanced concepts of resistance-based memories offer storage node scaling down below 10 nm, and the memory density will be limited by the select device.The select device thus represents a serious bottleneck for memory scaling to 10 nm and beyond.
26Suggested select device categories Select devicesTransistorPlanarVerticalDiodep-n junctionSchottky junctionHetero-junctionSwitch-based selectorMott transition switchThreshold switchResistive switchMixed ionic electronic conduction (MIEC)Complementary resistive switch structurePlacement of Rainer’s device in the table?
27Vertical Select Devices Vertical diodeVertical FETL. Li, K. Lu, B. Rajendran, T. D. Happ, H-L. Lung, C. Lam, and M. Chan, “Driving Device Comparison for Phase-Change Memory”, IEEE Trans. Electron. Dev. 58 (2011)
28Resistive-Switch-type select devices I Mott-transition switchis based on the Mott Metal-Insulator transitiona volatile resistive switch,A VO2-based Mott-transition device has been demonstrated as a selection device for NiOx RRAM element [Ref: M.J. Lee, “Two Series Oxide Resistors Applicable to High Speed and High Density Nonvolatile Memory,” Adv. Mater. 19, 3919 (2007).].The feasibility of the Mott-transition switch as selection devices still needs further research.Threshold switchis based the threshold switching in MIM structures caused by electronic charge injection/trappingSignificant resistance reduction can occur at a threshold voltage and this low-resistance state quickly recovers to the original high-resistance state when the applied voltage falls below a holding voltage.
29Resistive-Switch-type select devices II MIEC switchobserved in materials that conduct both ions and electronic charges – so called mixed ionic electronic conduction materials (MIEC).The resistive switching mechanism is similar to the ionic memories.Complementary resistive switchthe memory cell is composed of two identical non-volatile ReRAM switches connected back-to-back.Example: Pt/GeSe/Cu/GeSe/Pt structureDuring idle conditions one of the ReRAM switch is off so sneak current is reduced.Read involves turning on both ReRAM devices and is destructive.
30Benchmark Select Device Parameters ValueDriverON Voltage, Vr~1 VCompatibility with logic; low-power operationON current, Ir~10-6 ASensing of memory state (fast read)ON/OFF ratio*>106Sufficiently low ‘sneak’ currents **Operating temperature85°C50°CThe top end spec for servers. NAND spec (the very embodiment of non- volatile memory for the current state-of-the-art),*ON/OFF current ratio at ~(1V) supply**Proposed alternative schemes of array biasing could result in relaxed requirements on the select device ON/OFF ratio 
31Fundamental IssuesFor scaled diode-type select devices two fundamental challenges are:Contact resistanceLateral depletion effectsVery high concentration of dopants are needed to minimize both effects.high dopant concentrations result in increase reverse currents in classical diode structures and therefore in reduced ON/OFF ratio.For switch-type select devices the main challenges are:identifying the right materialand the switching mechanism to achieve the required drive current density, ON/OFF ratio and reliability.
32Select Devices Summary Experimental two-terminal select devices have yet to meet the benchmark specificationsHence, outstanding research issues persistMore detailed benchmarking and further analysis is needed
34New Section on SCM in 2011 ERD Storage-class memory (SCM) describes a device category that combines the benefits of solid-state memory, such as high performance and robustness, with the archival capabilities and low cost of conventional hard-disk magnetic storage.Such a device requires a nonvolatile memory technology that could be manufactured at a very low cost per bit.As the scalability of flash is approaching its limit, emerging technologies for non-volatile memories need to be investigated for a potential “take over” of the scaling roadmap for flash.In principle, such new SCM technology could engender two entirely new and distinct levels within the memory and storage hierarchy, located below off-chip DRAM and above mechanical storage, and differentiated from each other by access time.
35Prototypical and emerging memory technologies for SCM applications Necessary attributes of a memory device for the storage-class memory applications are:ScalabilityMultilevel Cell - MLC (MLC vs extreme scaling dilemma)3D integration (stacking)Fabrications costsEndurance (for M-SCM)Retention (for S-SCM)The driving issue is to minimize the cost per bit
36Potential of the current prototypical and emerging research memory candidates for SCM applications Prototypical (Table ERD3)Emerging (Table ERD5)ParameterFeRAMSTT-MRAMPCRAMEmerging ferroelectric memoryNanomechanical memoryRedox memoryMott MemoryMacromolecular memoryMolecular MemoryScalabilityMLC3D integrationFabrication costEndurance???????ScalabilityFmin >45 nmMLCdifficult3D integrationFabrication costhighEndurance≤1E5 write cycles demonstratedScalabilityFmin <10 nmMLCdifficult3D integrationFabrication costhighEndurance>1E10 write cycles demonstratedScalabilityFmin=10-45 nmMLCdifficult3D integrationFabrication costmediumEndurance≤1E10 write cycles demonstrated
37Plans for 2012For many memory entries, there are still lacking referenced parameter projections for several memory entriese.g. Mott memory, FTJ…The Memory Group will continue the fundamental studies to provide reasonable estimates of the missing dataIt would be helpful if fundamentals for all emerging memory devices could be elucidated in one source / single reference document containingcitationsbrief graphical/mathematical theory of operation with scaling limits projectionsa book project is currently under discussion by ERD editorial groupERD Memory Workshop (April 2012)Possible Topic: Memory Select DevicesNew ERD Memory candidates?