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Emerging Research Memory Devices: Status and 2012 plans

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1 Emerging Research Memory Devices: Status and 2012 plans
International ERD TWG Emerging Research Devices Working Group Face-to-Face Meeting Emerging Research Memory Devices: Status and 2012 plans Victor Zhirnov / SRC Washington, DC, December 4, 2011

2 Memory Team: An Chen (GLOBALFND)
Zoran Krivokapic(GLOBALFND) Al Fazio (Intel) Atsuhiro Kinoshita (Toshiba) U-In Chung (Samsung) Rich Liu (Macronix) Hiro Akinaga (AIST) Wei Lu (U Michigan) Dirk Wouters (IMEC) Kwok Ng (SRC) Thomas Vogelsang (RAMBUS) Matthew Marinella (Sandia Labs) Rainer Waser (Aachen U) Victor Zhirnov (SRC) Barry Schechtman (INSIC) Rod Bowman (Seagate) Geoff Burr (IBM) Bob Fontana (IBM) Michele Franceschini (IBM) Rich Freitas (IBM) Kevin Gomez (Seagate) Mark Kryder (CMU) Antoine Khroueir (Seagate) Kroum Stoev (Western Digital) Winfried Wilcke (IBM)

3 Input Received Alex Bratkovski (HP) Curt Richter (NIST)
Eric Pop (U Illinois) Table ERD5/Redox Memory Table ERD5/Redox Memory Table ERD4/PCM

4 Outline 2009-2011 Fundamental Studies
Review 2011 ERD memory tables and text Discussion on Specific Emerging Memory Devices Discussion of Memory Select Devices Discussion of Storage Class Memory Plans for 2012

5 2010-11 Important Events Emerging Research Memory Devices Workshop
Barza, Italy, April 2, 2008 Emerging Memory Materials workshop   Tsukuba, Japan, November 30, 2010 ERD Face-to-Face meeting   Potsdam, Germany, April 10, 2011 San Francisco, USA, July 10, 2006

6 ERD Memory Group Fundamental Studies in 2009-2011

7 2009 Challenge Lack of quantitative data
For many memory entries, there were no referenced scaling projections Optimistic expectations/claims were used to fill the ERD memory tables The ERD Memory Group decided to develop reference documents containing Brief theory of operation with scaling limits projections References to the state-of-the art ERD Memory activity focused on the development of quantitative data to support assessments of different memory entries To be continued in

8 ERD Memory Group Publishing Activity
Electronic Effects Memory RedOx (Ionic) Memory Memory Select Device H. Schroeder, V. V. Zhirnov, R. K. Cavin, R. Waser, Voltage-time dilemma of pure electronic mechanisms in resistive switching memory cells", JOURNAL OF APPLIED PHYSICS 107 (2010) Charge trapping induced resistive switching is not considered in 2011 ERD chapter, as a scaling of this memory technology below 100 nm is difficulty for any conceivable material combination V. V. Zhirnov, R. K. Cavin, S. Menzel, E. Linn, S. Schmelzer, D. Bräuhaus, C. Schindler and R. Waser, “Memory Devices: Energy-Space-Time Trade-offs”, Proc. IEEE 98 (Dec. 2010) 2185 V. V. Zhirnov, R. Meade, R. K. Cavin, S. Menzel, and G. Sandhu, “Scaling Limits of Resistive Memories”, Nanotechnology 22 (June 2011) Scaling and performance projections for <10nm ReRAM Wei Lu1, An Chen2, Kwok Ng3 and Victor V. Zhirnov3, “Select Devices for Extremely Scaled Memory Arrays”, in preparation 1University of Michigan ; 2GLOBALFOUNDRIES; 3Semicondcutor Research Corp.

9 2011 ERD Memory Tables and Text

10 2011 Memory Transition Table
IN/OUT (Table ERD5) Reason for IN/OUT Comment Emerging Ferroelectric Memory IN Replaces former FeFET category and the ferroelectric polarization/ electronic effects memory categories Ferroelectric polarization/ electronic effects memory has same difficult problems as FeFET, e.g. scalability, retention, endurance fatigue Redox memory Replaces former nanothermal and Ionic memory categories   Former ‘Nanothermal’ and ‘Nanoinic’ entries often referred to related mechanisms of resistive switching Mott Memory Separated from the electronic effects memory FeFET Memory OUT Merged with FeFET and the ferroelectric polarization/electronc effects memory Electronic effects memory Replaced by EFM and Mott Nanothermal memory Merged with Ionic Memory to form Redox Memory Category Nanoionic memory Merged with Nanothermal Memory to form Redox Memory Category  Related mechanism to Nanothermal memory Spin Torque Transfer MRAM Became a prototypical technology Spin Torque Tranfer MRAM is already included in PIDS chapter since 2009 (Tables PIDS5 and PIDS 5A)

11 2011 ERD Memory Table Emerging Ferroelectric memory
Emerging Ferroelectric memory Nanomechanical Memory Redox Memory Mott Memory Macromolecular Memory Molecular Memories Storage Mechanism Remnant polarization on a ferroelectric gate dielectric Electrostatically-controlled mechanical switch Ion transport and Multiple mechanisms redox reaction Cell Elements 1T or 1T1R 1T1R or 1D1R Device Types FET with FE gate insulator FTJ 1) nanobridge 1) cation migration M-I-M (nc)-I-M Bi-stable switch 2) telescoping CNT 2) anion migration Mott transition 3) Nanoparticle

12 Emerging Ferroelectric Memory
In 2011 ERD combines two subcategories: Ferroelectric FET Ferroelectric tunnel junction (FTJ) Motivation for merging Operation principle of FTJ is based on ferroelectric polarization, similar to FeFET Same difficult problems as in FeFET Retention, endurance fatigue, scalability This merging did not work well: The physics of READ and WRITE are very different for FeFET and FTJ memories Difficult to display the performance data in one column Proposal: To split FeFET and FTJ in two separate entries in 2013

13 Ferroelectric FET & memory
Number of publications (94+23) FeFET FTJ

14 Nanomechanical Memory (NEMM)
Difficult Challenges Scalability W. Y. Choi, T. Osabe and T-S. K. Liu, “Nano-electro-mechanical nonvolatile memory (NEMory) cell design and scaling”, IEEE Trans. Electron Dev. 55 (2008) Reliability/Endurance typically fail after ~100 switching cycles [B4] J-W. Han, J-H. Ahn, Y-K. Choi, "FinFACT - fin flip-flop actuated channel transistor", IEEE Electron Dev. Lett. 31 (2010) 764 J. Andazane et al., “Two-terminal nanoelectromechanical devices based on germanium nanowires”, Nano Lett. 9 (2009) 1824 K. Lee and W. Y. Choi, “Nanoelectromechanical Memory Cell (T Cell) for Low-Cost Embedded Nonvolatile Memory Applications”, IEEE Trans. Electron Dev. 58 (2011) O. Loh; X. Wei; C .Ke; et al. “Robust Carbon-Nanotube-Based Nano-electromechanical Devices: Understanding and Eliminating Prevalent Failure Modes Using Alternative Electrode Materials”, SMALL 7 (2011) 79-86 Y. Choi and T-J. K. Liu, “Reliability of nanoelectromechanical nonvolatile memory (NEMory) cells”, IEEE Electron Dev. Lett. 30 (2009) Best projected >50 nm [B1, B2] Demonstrated 500 nm [B3, B4] Low voltage (~ 1V) operation Demonstrated ~1E3 [B4] Should NEMM be in ERD in 2013?

15 Nanomechanical Memory (NEMM)
Number of publications

16 RedOx Memory Former ‘Nanothermal’ and ‘Nanoinic’ entries often referred to related mechanisms of resistive switching Recent experimental demonstrations of scalability, retention and endurance are encouraging Many details of the mechanism of the reported phenomena are still unknown Number of publications (+30+44) (+99+77)

17 Mott Memory A new entry in 2011
More research on the size effect of the Mott transition properties is needed to address the fundamental scaling limit of this type of devices. What is the minimum number of atoms in a Mott memory element to provide retention and sensing properties? Needs to be investigated under benchmark values

18 Mott memory recent publications
D. Ruzmetov, G. Gopalakrishnan, J. Deng, V. Narayanamurti, S. Ramanathan, “Electrical triggering of metal-insulator transition in nanoscale vanadium oxide junctions”, J. Appl. Phys. 106 (2009) S. D. Ha, G. H. Aydogdu, and S. Ramanathan, “Metal-insulator transition and electrically driven memristive characteristics of SmNiO3 thin films”, Appl. Phys Lett. 98 (2011) K-H. Xue, C. A. Paz de Araujo, J. Celinska, C. McWilliams, “A non-filamentary model for unipolar switching transition metal oxide resistance random acess memories”, J. Appl. Phys. 109 (2011) J. Celinska, C. McWilliams, C. Paz de Araujo, K-H. Xue, “Material and process optimization of correlated electron random access memories”, J. Appl. Phys. 109 (2011) C. R. McWilliams, J. Celinska, C. A. Paz de Araujo, K-H. Xue, “Device characterization of correlated electron random access memories”, J. Appl. Phys.109 (2011) L. Cario, C. Vaju, B. Corraze, V. Guiot, E. Janod, “Electric-field-induced resistive switching in a family of Mott Insulators: Toward a new class of RRAM memories”, Adv. Mat. 22 (2010) M. K. Niranjan, Y. Wang, S. S. Jaswal, and E. Y. Tsymbal, “Prediction of a switchable two-dimensional electron gas at ferroelectric oxide interfaces’, Phys. Rev. Lett. 103 (2009) 20 publications in

19 Macromolecular Memory
Also referred to as polymer or organic resistive memory Consists of a film of organic material sandwiched between two metal electrodes The organic film is typically relatively thick (~many monolayers) Reduced fabrication cost is often considered as the primary driver for this type of memory Extreme scaling is de-emphasized Mechanism of operation is not clear There are some indications on the RedOx effects Possible transition to the RedOx Memory category?

20 Macromolecular Memory
Number of publications

21 Molecular Memory A broad term encompassing different proposals for using individual molecules or small clusters of molecules as building blocks of memory cells. The concept emphasizes extreme scaling in principle, one bit of information can be stored in the space of a single molecule The success of molecular electronics depends on our understanding of the phenomena accompanying molecular switching, currently many questions remain unanswered Molecular memory is viewed as a long term research goal

22 Molecular Memory Number of publications 2001-2003 43 2003-2005 68

23 ERD Memory: Research Activity
RedOx Macromolecular Molecular FeFET NEMM

24 Memory Select Device

25 Memory Select Device: Intro
A memory cell in array can be viewed as being composed of two fundamental components: the ‘Storage node’, and the ‘Select device’ to minimize sneak current through unselected cells. Both components impact scaling limits for memory. Several advanced concepts of resistance-based memories offer storage node scaling down below 10 nm, and the memory density will be limited by the select device. The select device thus represents a serious bottleneck for memory scaling to 10 nm and beyond.

26 Suggested select device categories
Select devices Transistor Planar Vertical Diode p-n junction Schottky junction Hetero-junction Switch-based selector Mott transition switch Threshold switch Resistive switch Mixed ionic electronic conduction (MIEC) Complementary resistive switch structure Placement of Rainer’s device in the table?

27 Vertical Select Devices
Vertical diode Vertical FET L. Li, K. Lu, B. Rajendran, T. D. Happ, H-L. Lung, C. Lam, and M. Chan, “Driving Device Comparison for Phase-Change Memory”, IEEE Trans. Electron. Dev. 58 (2011)

28 Resistive-Switch-type select devices I
Mott-transition switch is based on the Mott Metal-Insulator transition a volatile resistive switch, A VO2-based Mott-transition device has been demonstrated as a selection device for NiOx RRAM element [Ref: M.J. Lee, “Two Series Oxide Resistors Applicable to High Speed and High Density Nonvolatile Memory,” Adv. Mater. 19, 3919 (2007).]. The feasibility of the Mott-transition switch as selection devices still needs further research. Threshold switch is based the threshold switching in MIM structures caused by electronic charge injection/trapping Significant resistance reduction can occur at a threshold voltage and this low-resistance state quickly recovers to the original high-resistance state when the applied voltage falls below a holding voltage.

29 Resistive-Switch-type select devices II
MIEC switch observed in materials that conduct both ions and electronic charges – so called mixed ionic electronic conduction materials (MIEC). The resistive switching mechanism is similar to the ionic memories. Complementary resistive switch the memory cell is composed of two identical non-volatile ReRAM switches connected back-to-back. Example: Pt/GeSe/Cu/GeSe/Pt structure During idle conditions one of the ReRAM switch is off so sneak current is reduced. Read involves turning on both ReRAM devices and is destructive.

30 Benchmark Select Device Parameters
Value Driver ON Voltage, Vr ~1 V Compatibility with logic; low-power operation ON current, Ir ~10-6 A Sensing of memory state (fast read) ON/OFF ratio* >106 Sufficiently low ‘sneak’ currents ** Operating temperature 85°C 50°C The top end spec for servers.  NAND spec (the very embodiment of non- volatile memory for the current state-of-the-art), *ON/OFF current ratio at ~(1V) supply **Proposed alternative schemes of array biasing could result in relaxed requirements on the select device ON/OFF ratio [5]

31 Fundamental Issues For scaled diode-type select devices two fundamental challenges are: Contact resistance Lateral depletion effects Very high concentration of dopants are needed to minimize both effects. high dopant concentrations result in increase reverse currents in classical diode structures and therefore in reduced ON/OFF ratio. For switch-type select devices the main challenges are: identifying the right material and the switching mechanism to achieve the required drive current density, ON/OFF ratio and reliability.

32 Select Devices Summary
Experimental two-terminal select devices have yet to meet the benchmark specifications Hence, outstanding research issues persist More detailed benchmarking and further analysis is needed

33 Storage Class Memory

34 New Section on SCM in 2011 ERD
Storage-class memory (SCM) describes a device category that combines the benefits of solid-state memory, such as high performance and robustness, with the archival capabilities and low cost of conventional hard-disk magnetic storage. Such a device requires a nonvolatile memory technology that could be manufactured at a very low cost per bit. As the scalability of flash is approaching its limit, emerging technologies for non-volatile memories need to be investigated for a potential “take over” of the scaling roadmap for flash. In principle, such new SCM technology could engender two entirely new and distinct levels within the memory and storage hierarchy, located below off-chip DRAM and above mechanical storage, and differentiated from each other by access time.

35 Prototypical and emerging memory technologies for SCM applications
Necessary attributes of a memory device for the storage-class memory applications are: Scalability Multilevel Cell - MLC (MLC vs extreme scaling dilemma) 3D integration (stacking) Fabrications costs Endurance (for M-SCM) Retention (for S-SCM) The driving issue is to minimize the cost per bit

36 Potential of the current prototypical and emerging research memory candidates for SCM applications
Prototypical (Table ERD3) Emerging (Table ERD5) Parameter FeRAM STT-MRAM PCRAM Emerging ferroelectric memory Nanomechanical memory Redox memory Mott Memory Macromolecular memory Molecular Memory Scalability MLC 3D integration Fabrication cost Endurance ? ? ? ? ? ? ? Scalability Fmin >45 nm MLC difficult 3D integration Fabrication cost high Endurance ≤1E5 write cycles demonstrated Scalability Fmin <10 nm MLC difficult 3D integration Fabrication cost high Endurance >1E10 write cycles demonstrated Scalability Fmin=10-45 nm MLC difficult 3D integration Fabrication cost medium Endurance ≤1E10 write cycles demonstrated

37 Plans for 2012 For many memory entries, there are still lacking referenced parameter projections for several memory entries e.g. Mott memory, FTJ… The Memory Group will continue the fundamental studies to provide reasonable estimates of the missing data It would be helpful if fundamentals for all emerging memory devices could be elucidated in one source / single reference document containing citations brief graphical/mathematical theory of operation with scaling limits projections a book project is currently under discussion by ERD editorial group ERD Memory Workshop (April 2012) Possible Topic: Memory Select Devices New ERD Memory candidates?

38 Different ERD Memory Entries
Number of entries

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