Presentation on theme: "Circuit Modeling of Non-volatile Memory Devices"— Presentation transcript:
1 Circuit Modeling of Non-volatile Memory Devices M. Sadd and R. MuralidharIntroduction to NVMCapacitor sub-circuit and sense modelExtensions: Program/Erase, 2-bit storage, reliability
2 NVM operates with processes that normally cause failure: Example NVM ProcessFailure ModeFe-RAMFerro-Electric HysteresisVt instability in High-k dielectricsSONOSCharge Trapping in gate stackFixed Charge instabilityFloating Gate NVMHCI Programming/ Tunnel EraseStress-induced trap creation and chargingNeed to model effects that are minimized in most other devices!
3 Flash Cell Over-view Flash Cell most common type of NVM: Control GateONO LayerFloating GateTunnel OxideThe memory becomes “Flash” when organized in an array with “block” erase:NOR Array:
4 Flash Cell Operations Operation: Sense Program Erase Retention Model Needs to describe:Variable Threshold voltageHCI or TunnelingTunnelingCharge loss
5 Flash Sense Operation Memory senses the Vt shift from stored charge: Basic sense circuit:
6 Flash Sense ModelSimple Approach Separate models for program/erase VtMore flexible sub-circuit:
8 Sense Model: Extraction VdVgExtract base MOSFET model by accessing floating gateCompare to bit-cell to obtain coupling capacitancesVgVdRequires comparison of two devices subject to mis-match errorsExtraction with bit-cell alone (e.g. ref) requires erase or program model
9 Flash Sense Model: Use Model may only be used for transient simulation Example: Generating an Id-Vg curveRamp Drain from 0 to VdRamp Gate from 0 to VgCompute IdrainIdrain vs. Vgate Ramp slow enough that transient currents (C dV/dt) ~ 0Not restrictive: Model used mainly for timing
10 Flash Sense Model: DC Model May build a DC Flash model:Solve for Floating node potential for capacitor sub-circuit modelSee:Y. Tat-Kwan, et. al. IEDM Tech Dig. p. 157 (1994)L. Larcher, et. al. IEEE Trans. Elec. Dev., 49 p. 301(2002) Voltage source sets Vfg such that charge QFG is conserved
11 Flash Program/Erase Model Time scales:Read ~ 10 nsProgram ~ 1 sErase ~ 100 msRetention ~ 10 YearsRead tightest timing, so most need for circuit simulationProgram/Erase May need a circuit model (multi-level storage)Most models add non-linear resistor or current source:
12 Charge-Trapping NVM Scaled NVM devices charge trapping in a layer of: Nitride (SONOS): Nano-crystals:Advantages:Reliability (resistant to defects)Reduced program/erase voltageAvoids drain coupling “DIBL”
13 Charge-Trapping NVM: 2 Bit Storage Two bits may be stored: One each above source or drain:For large Vd charge over source barrier affects charge more than over drainA simple circuit model:Two reads (forward & reverse) can store 4 states:Forward VtReverse VtStateHigh11Low100100
14 Reliability Model Non-linear current source model charge loss: Integrate in log(t)dQ/d(log(t)) = t dQ/dt = t Itunnel(V) May calculate long-time loss:Physics of charge loss (tunneling) is lumped into the non-linear current source
15 Summary Capacitor sub-circuit foundation for flash model Appropriate for timing simulationMay be augmented to model:Program and eraseReliability (charge loss or gain)Device asymmetry (2-bit storage)
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