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Circuit Modeling of Non-volatile Memory Devices M. Sadd and R. Muralidhar 1.Introduction to NVM 2.Capacitor sub-circuit and sense model 3.Extensions: Program/Erase,

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Presentation on theme: "Circuit Modeling of Non-volatile Memory Devices M. Sadd and R. Muralidhar 1.Introduction to NVM 2.Capacitor sub-circuit and sense model 3.Extensions: Program/Erase,"— Presentation transcript:

1 Circuit Modeling of Non-volatile Memory Devices M. Sadd and R. Muralidhar 1.Introduction to NVM 2.Capacitor sub-circuit and sense model 3.Extensions: Program/Erase, 2-bit storage, reliability

2 NVM operates with processes that normally cause failure: ExampleNVM ProcessFailure Mode Fe-RAM Ferro-Electric Hysteresis V t instability in High-k dielectrics SONOS Charge Trapping in gate stack Fixed Charge instability Floating Gate NVM HCI Programming/ Tunnel Erase Stress-induced trap creation and charging Need to model effects that are minimized in most other devices!

3 Flash Cell Over-view Flash Cell most common type of NVM: The memory becomes Flash when organized in an array with block erase: NOR Array: Control Gate Floating Gate ONO Layer Tunnel Oxide

4 Flash Cell Operations Operation: Sense Program Erase Retention Model Needs to describe: Variable Threshold voltage HCI or Tunneling Tunneling Charge loss

5 Flash Sense Operation Memory senses the V t shift from stored charge: Basic sense circuit:

6 Flash Sense Model Simple Approach Separate models for program/erase V t More flexible sub-circuit:

7 Flash Sense Model Charge stored on floating node: Q FG ~ C mos V fg + C fs V fg + C fd (V fg - V d ) + C cg (V fg -V cg ) Define coupling ratios: g = C cg / (C cg + C mos + C fd + C fs ) d = C fd / (C cg + C mos + C fd + C fs ) Then, V T ~ -Q FG /C cg + (1/ g ) V T,FG + ( d / g ) V d Charge of floating node shifts V t Drain coupling to floating gate introduces DIBL Typically g = and d ~ 0.1

8 Sense Model: Extraction 1.Extract base MOSFET model by accessing floating gate 2.Compare to bit-cell to obtain coupling capacitances Requires comparison of two devices subject to mis- match errors Extraction with bit-cell alone (e.g. ref) requires erase or program model VdVd VgVg VdVd VgVg

9 Flash Sense Model: Use Model may only be used for transient simulation Example: Generating an Id-Vg curve 1.Ramp Drain from 0 to V d 2.Ramp Gate from 0 to V g 3.Compute I drain 4.I drain vs. V gate Ramp slow enough that transient currents (C dV/dt) ~ 0 Not restrictive: Model used mainly for timing

10 Flash Sense Model: DC Model May build a DC Flash model: See: Y. Tat-Kwan, et. al. IEDM Tech Dig. p. 157 (1994) L. Larcher, et. al. IEEE Trans. Elec. Dev., 49 p. 301(2002) Voltage source sets V fg such that charge Q FG is conserved Solve for Floating node potential for capacitor sub- circuit model

11 Flash Program/Erase Model Time scales: Read ~ 10 ns Program ~ 1 s Erase ~ 100 ms Retention ~ 10 Years Read tightest timing, so most need for circuit simulation Program/Erase May need a circuit model (multi-level storage) Most models add non-linear resistor or current source:

12 Charge-Trapping NVM Scaled NVM devices charge trapping in a layer of: Nitride (SONOS):Nano-crystals: Advantages: Reliability (resistant to defects) Reduced program/erase voltage Avoids drain coupling DIBL

13 Charge-Trapping NVM: 2 Bit Storage Two bits may be stored: One each above source or drain: A simple circuit model: For large V d charge over source barrier affects charge more than over drain Forward V t Reverse V t State High 11 HighLow10 LowHigh01 Low 00 Two reads (forward & reverse) can store 4 states:

14 Reliability Model Non-linear current source model charge loss: Integrate in log(t) dQ/d(log(t)) = t dQ/dt = t I tunnel (V) May calculate long-time loss: Physics of charge loss (tunneling) is lumped into the non- linear current source

15 Summary Capacitor sub-circuit foundation for flash model Appropriate for timing simulation May be augmented to model: Program and erase Reliability (charge loss or gain) Device asymmetry (2-bit storage)


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