Presentation on theme: "EET 252 Unit 5 Programmable Logic: FPGAs & HDLs Read Floyd, Sections 11-5 to 11-10. Study Unit 5 e-Lesson. Do Lab #5. Lab #5a due next week. "— Presentation transcript:
EET 252 Unit 5 Programmable Logic: FPGAs & HDLs Read Floyd, Sections 11-5 to 11-10. Study Unit 5 e-Lesson. Do Lab #5. Lab #5a due next week. Homework #5 and Lab #5b due in two weeks. Midterm exam next week.
FPGAs compared to CPLDs CPLDsFPGAs Based on programmable AND array and fixed OR array. Based on look-up table (LUT), which is basically a truth table. (Results in higher density.) Usually EEPROM technology, so non- volatile. Usually SRAM technology, so volatile. Both are programmed using the same software, using either schematic entry or text entry.
FPGA Cores Most SPLDs and CPLDs are completely blank when you buy them. Because FPGAs are so dense, many chip-makers give the option of manufacturing some of the circuitry to perform a specific function, such as a microprocessor or a RAM. Such pre-programmed circuitry is called a core.
Hard Core, Soft Core, IP A hard core is a core that cannot be reprogrammed by the user. A soft core is a core that the user can reprogram to some extent. Cores are also referred to as intellectual property (IP), since the chip-maker retains ownership of the core design. Example on Altera’s website. Example on Altera’s website.
Hardware Description Languages (HDLs) Many hardware description languages (HDLs) exist for text entry of PLD designs. Learning an HDL takes longer than learning to do schematic entry. But for complex designs it can provide a more powerful and simpler way to enter designs.
Some Popular HDLs Open-standard HDLs VHDL (IEEE 1076) Verilog (IEEE 1364) Proprietary HDLs CUPL ABEL (Advanced Boolean Expression Language, now owned by Xilinx) AHDL (Altera HDL)
JTAG (IEEE 1149.1) Registers and I/O Signals Registers Boundary scan register Bypass register Instruction register Optional: Identification register I/O Signals TDI (Test Data In) TDO (Test Data Out) TMS (Test Mode Select) TCK (Test Clock) Optional: TRST (Test Reset) See pp. 4-5 of Altera UP1 Board manual (on course website). See pp. 4-5 of Altera UP1 Board manual (on course website).