1. FPGA Based Fuzzy Logic Controller for Semi- Active Suspensions Aws Abu-Khudhair

2. ENGG 65302 Outline Types of Suspension Systems Project Objective

3. DSP and Reconfigurable Computing Systems Aws Abu-Khudhair

4. ENGG 65304 Outline What is DSP?... Implementation of Various Algorithms… Advantages of FPGA in DSP… Tools available/Mapping DSP onto FPGA…

5. Aws Abu-KhudhairENGG 65305 Resources [1] “A Primer on FPGA-Based DSP Applications”, by Acromag Inc. [2] “Designing Digital Signal Processing with FPGAs”, by Allen Kinast [3] “FPGA Implementations of Fast Fourier Transforms for Real-Time Signal and Image Processing”, by I.S. Uzun, A. Amira and A. Bouridane [4] “Choosing the Right Architecture for Real- Time Signal Processing Designs”, by Leon Adams. [5] “Digital Signal Processors: Applications and Architectures”, by Kurt Keutzer

6. Aws Abu-KhudhairENGG 65306 What is DSP? Concerned with the manipulation of signals for: –Filtering –Transformation –Decoding/Encoding etc. Widely implemented in PDSP

7. Aws Abu-KhudhairENGG 65307 DSP Applications Wireless Communication Audio Applications Image Processing/Medical Imaging Networking Weather forecasting

8. Aws Abu-KhudhairENGG 65308 Various Algorithms Finite Impulse Response (FIR) filters Fast Fourier Transforms (FFT) Infinite Impulse Response (IIR) filters Forward Error Correction (FEC) Modulation/Demodulation

9. Aws Abu-KhudhairENGG 65309 DSP Implementation Comparison TechnologyPerformanceCostPowerFlexibilityDesign Effort GPPLow MediumHighLow PDSPMedium FPGAMed-HighMediumLow-MedHighMedium ASICHigh Low High Most suitable technology??

10. Aws Abu-KhudhairENGG 653010 PDSP vs. FPGA PDSP –Specialized microprocessor based on the Von Neumann arch. –Programmed in C/assembly for performance –Suited for complex math-intensive tasks, with conditional processing. –Limited in performance by the clock rate and number of operations it can perform per clock cycle. e.g. TMS320C6201 has 2 multipliers + 200MHz clock  400M multipliers/second

11. Aws Abu-KhudhairENGG 653011 PDSP vs. FPGA cont. FPGA –Uncommitted gates –Programmed by HDL. –Performance limited by the number of gates and clock rate. –Suited for a wide range of applications

12. Aws Abu-KhudhairENGG 653012 Advantages/Disadvantages of FPGA Advantages –Parallel Processing (Performance) –Flexible Architecture –Price –Power Demand compared to DSP Disadvantages –Higher development cost and increased time to market than DSP –Implementation of conditional processing

13. Aws Abu-KhudhairENGG 653013 Important Building Blocks Add Subtract Multiply Multiply and Add Multiply and Accumulate (MAC) Unit Data Out Reg MAC unit Coefficient

14. Aws Abu-KhudhairENGG 653014 256 Tap FIR Filter 256 Loops needed to process samples 1 FIR tap per DSP instruction cycle Conventional DSP – Serial processing

15. Aws Abu-KhudhairENGG 653015 256 Tap FIR Filter cont. All 256 MAC operations in 1 clock cycle FPGA – Parallel processing

16. Aws Abu-KhudhairENGG 653016 FPGA Design Flexibility FPGA – Design Optimization × × × × + + + + + + × + + D Q × × + + + + Parallel Semi-ParallelSerial Speed Cost Q = (A x B) + (C x D) + (E x F) + (G x H) Multiply and Add

17. Aws Abu-KhudhairENGG 653017 Performance of PDSP VS. FPGA Feature Conventional PDSP Virtex –II Virtex –II pro Spartan-3 8 x 8 Multiply Accumulate (MAC) 5.7 billion MAC/s 0.5 Tera MAC/s 1 Tera MAC/s 0.27 Tera MAC/s FIR Filter - 256 taps, linear phase - 16-bit data/coefficients 11.16 MSPS 720 MHz 180 MSPS 180 MHz 300 MSPS 300 MHz 140 MSPS 140 MHz Complex FFT - 1024 point, 16-bit data 8.5  s 720 MHz 0.914  s 140 MHz 0.853  s 150 MHz 0.914  s 140 MHz

18. Aws Abu-KhudhairENGG 653018 Advanced FPGA Architectures with DSP Resources FeaturesVirtex-4Startix IIECP-DSP Clock Management DCM – up to 20 PLL – up to 12 sysCLOCK PLL – up to 4 Embedded Memory BlockRAM up to 10 Mb TriMatrix memory up to 9 Mb sysMEM blocks up to 498 Kb Data Processing Up to 200K CLBs & 512 XtremeDSP Slices Up to 179K LEs, 384 Embedded multipliers & 96 DSP blocks Up to 4096 PFUs, 32 multiplier blocks & 8 DSP blocks Clock SpeedUp to 500 MHz Up to 250 MHz

19. Aws Abu-KhudhairENGG 653019 DSP Design tools C, C++ MATLAB / Simulink HDL (VHDL / Verilog) Xilinx EDK/ISE

20. Aws Abu-KhudhairENGG 653020 MATLAB / Simulink

21. Aws Abu-KhudhairENGG 653021 Simulink

22. Aws Abu-KhudhairENGG 653022 Simulink + ISE

23. Aws Abu-KhudhairENGG 653023 Design flow with FPGA

24. Aws Abu-KhudhairENGG 653024 DSP Design Evolution from HW DSP to FPGA DSP solutions 1.Signal capture and sync. 2.Data exchange methodology 3.off-the shelf hardware 4.Logic Processing 5.Price/Feature 6.Data/Sample rates 7.Debugging 8.Use of IP cores 9.I/O interface 10.Development cycles 11.Deployment cost

25. Aws Abu-KhudhairENGG 653025 Conclusion “The primary reason solutions were so expensive to design, slow to develop and prove, and difficult to re-deploy was that the solutions were fixed in hardware” [1]

26. Aws Abu-KhudhairENGG 653026 Questions? Thank you