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DSPs Vs General Purpose Microprocessors AOE 5984 – Real Time Systems.

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Presentation on theme: "DSPs Vs General Purpose Microprocessors AOE 5984 – Real Time Systems."— Presentation transcript:

1 DSPs Vs General Purpose Microprocessors AOE 5984 – Real Time Systems

2 Common DSP Applications…  Communications  Audio, Video processing  Graphics, 3-D rendering  Navigation, radars, GPS  Controls – Robotics, guidance, Machine Vision  Filtering  Frequency-Time transformations (FFT-IFFT)

3 Common DSP Tasks…  Modulation-Demodulation, Error correction  Noise reduction, equalization, echo cancellation  Audio compression  Vector and Matrix calculations  Control algorithms

4 DSPs Need to Do…  Efficient repetitive numerical calculations  Maintain numeric fidelity  Provide high memory bandwidth  Streaming data  Real Time processing

5 DSPs Need to Minimize…  Real Time execution unpredictability  Memory use  Power consumption  Cost  Development time

6 What Do DSPs Have?  Specialized memory architecture (Harvard)  Specialized parallel execution units  Specialized addressing modes  Specialized instruction sets for parallel execution  Specialized peripherals

7 FIR Filtering… D x h0h0 D h1h1 D hnhn y 1.Two data fetches, 2.Multiply operation, 3.Accumulate Operation, 4.Input vector shifting

8 Multiply-Accumulate (MAC) Multiplication in single cycle Execution time ~ 200 ns Register Multiplier ALU Accumulator

9 Special Hardware Units… Hardware shifter. Hardware circular buffers. Special h/w for zero overhead looping. Special address generation units.

10 Address Generation Units… Work in parallel with DSP core execution unit. Access new addresses without pausing to calculate new addresses. Take advantage of predictability in the pattern of data access in DSP algorithms, using special addressing modes. e.g. register-indirect with post increment addressing, circular (modulo) addressing, bit- reverse addressing in hardware.

11 Von Neumann Architecture… Processor Core Memory (Code+Data) Address bus Data bus 1.Fetch MAC instruction 2.Read value of ‘x’ 3.Read value of ‘h’ 4.Multiply x, h and accumulate 5.Write result to memory 4 memory access operations One multiplication

12 Harvard Architecture… Processor Core Memory B 1.Data and Code in separate memory segments 2.Multiple address and data buses 3.Double memory bandwidth 4.Simultaneous code and data fetch Memory A AB1 AB2 DB1 DB2

13 Caches in DSP and GPP… 1.GPPs normally contain two on-chip caches – one for data and the other for instructions. 2.Allows full speed retrieval of instructions and data without accessing slower off-chip memory. 3.DSPs contain a very small instruction cache and no data cache. 4.GPPs use control logic to determine what code and data goes into cache, while in DSPs it is programmer’s job to make a decision.

14 Fixed-Point Arithmetic… Most DSPs use fixed point arithmetic than floating point. Faster. Cheaper. Hardware support for saturation arithmetic, rounding and shifting.

15 Special Instructions Why special instructions? Multiple operations per instruction cycle. Minimize program memory space. Specify several parallel operations in a single instruction. These instructions permit restricted access to registers and do not allow arbitrary operation combinations.

16 Special Instructions… MAC X0, Y0, A, X: (R0)+,X0, Y:(R4)+N4, Y0 Multiply contents of X0 and Y0 Add result to accumulator A Load register X0 from X memory location pointed to by R0 Load register Y0 from Y memory location pointed to by R4 Post-increment R0 by 1 Post-increment R4 by the contents of register R4 This instruction calculates one tap of the FIR filter in one clock cycle

17 Execution Time Predictability… Non-DSP applications have a maximum average response time (firm real time). DSP applications are hard real time. Important to be able to calculate exactly the processing time required, or at least the worst time scenario. GPPs do not have a good execution time predictability. Lack of execution time predictability affect code optimization.

18 Execution Time Predictability… GPPs – complicated algorithms for branch prediction and caching. Speculative code execution depending on branch prediction. Programmer does not know which instructions and data will go into cache and when. Worst case execution time may be a order of magnitude greater than the actual execution time.

19 Execution Time Predictability… DSPs do not use branch prediction algorithms. Programmer decides which instruction go into cache. No data cache in most DSPs.

20 Other features of DSPs and GPPs VLIW (Very Long Instruction Word). Combines a number of different instructions in a long instruction word. e.g. 256 bytes word – 8 instructions. More MACs, ALUs and other execution units. GPPs use SIMD.

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