1. CPT Week, April 2001Darin Acosta1 Status of the Next Generation CSC Track-Finder D.Acosta University of Florida

2. CPT Week, April 2001Darin Acosta2 Track-Finder Crate Tests è Last Fall we successfully tested a complete chain of prototypes, yielding perfect agreement with the simulation for millions of events è Documented in TDR, with detailed Note to follow SPSR CCB Bit3 VME Interface Custom backplane MPC 100m optical fibers

3. CPT Week, April 2001Darin Acosta3 A Compact Muon Trigger The next step is to reduce the CSC latency by consolidating several boards and chips and by increasing the clock frequency to 80 MHz è New 1.6 Gbit optical link technology: p Texas Instruments TLK2501 80 MHz serializer & new optics p Reduces connections from peripheral crate (1  / link) so that all receivers can fit onto one board è Synchronous pipelined SRAM: p Samsung, IDT p Allows LUTs on Sector Receiver to operate at  80 MHz in order to reduce chip count è High Density FPGAs: p 2.5M gates with Xilinx Virtex XCV2000E p Fits all 17 FPGAs + LUTs of Sector Processor into one chip Thus, the entire CSC Track-Finder can fit into 1 crate

4. CPT Week, April 2001Darin Acosta4 Possible Crate Layout 15

5. CPT Week, April 2001Darin Acosta5 Possible Board Layout

6. CPT Week, April 2001Darin Acosta6 SR/SP Inputs è Muon Port Cards deliver 15 track stubs each BX via optical è DT Track-Finder delivers 2 track stubs each BX via LVDS Delivers 240 bits @ 80 MHz

7. CPT Week, April 2001Darin Acosta7 SR/SP Outputs è 6 track stubs are delivered to DT Track-Finder each BX via LVDS (can we multiplex at 80 MHz to save connector space?) è 3 muons per SP are delivered to Muon Sorter via GTLP backplane

8. CPT Week, April 2001Darin Acosta8 SR Memory Scheme è Use cascaded synchronous SRAM to accomplish transformation of LCT bit patterns into global tracking variables p Includes alignment corrections è Multiplex muons @ 80 MHz to reduce chip count to ~45

9. CPT Week, April 2001Darin Acosta9 Pipelined Memory Tests Developed small evaluation board to test two pipelined memories in series è Samsung 1M x 18 synch. SRAM (K7A161800M) è Include scheme to multiplex two muon stubs through same memory set @ 80 MHz Tested chips up to 150 MHz and encountered no errors with random number inputs è Specified maximum frequency is 180 MHz Low power è ~1W per memory at 150 MHz Latency determination è 2 clocks per memory (4 clocks for two in series) è 7 clocks total including 80 MHz serialization and de-serialization of muon stubs  3.5 BX @ 80 MHz p May be possible to shave 0.5 BX

10. CPT Week, April 2001Darin Acosta10 SR Memory Prototype Tested hardware Simulation illustrating clocking of board

11. CPT Week, April 2001Darin Acosta11 SR Latency Estimate @ 80 MHz Optical links (T.I.) è 76 – 82 ns latency for serialization and de-serialization of one frame, + 0.5 BX to wait for second frame of data è Therefore, ~2 BX for receiving complete muon stub in SR (was 2 BX for HP Glink as well) Track stub conversion è 3.5 BX (was 2 BX in last prototype  +1.5 BX) è Includes track stub serialization/de-serialization @ 80 MHz and propagation through two memories Total latency is 5.5 BX è Compare to 4 BX of last prototype  +1.5 BX However, this estimate is conservative è Possible to process track stub data off optical link without waiting for second frame p Saves 0.5 BX – 1 BX by not waiting & removing some logic p Judicious choice of data in first frame of optical link, and new LUT scheme è Could run clock for synch. SRAM at 120 or 160 MHz

12. CPT Week, April 2001Darin Acosta12 SP in a Chip Study Feasibility study was performed to fit all Sector Processor logic into one FPGA è Merged all separate schematics from current SP prototype into one project (17 FPGAs) è Transformed large Track Assembler LUTs into a Verilog algorithm for FPGA è Utilized 63% of the resources of a Xilinx Virtex-E (XCV1600EFG680-8) è Simulation shows that the latency of the SP logic is 11 BX at a maximum frequency of 41 MHz p Add 1 BX for final P T Assignment LUT p Compare to 15 BX of current SP prototype  save 3 BX è ChannelLink between SR and SP removed (save 4 BX more) è Improvement to total SR+SP latency  save at least 5.5 BX è SP Chip I/O: p ~300 input bits (80 MHz) p ~100 output bits (40 MHz)

13. CPT Week, April 2001Darin Acosta13 Backplane Development First CSC TF backplane technology was ChannelLink è It worked ! Serialization reduced ~600 signals into 200 for SP è Latency is long: 4 clocks Next generation backplane technology will be GTLP è No differential signals (fewer traces) è We have tested a small prototype backplane with GTLP signals p It works: tested drivers from Fairchild, and Xilinx Virtex I/O è We have developed and produced a full 21 slot custom VME backplane for use in the CSC front-end peripheral crate p Includes 40 MHz bussed signals and 80 MHz point-to-point p Highest density is ~660 signals into Muon Port Card (vs. ~680 signals into CSC Muon Sorter in CSC TF crate) multiplexed at 80 MHz p Have tested bussed signals with backplane fully loaded 

14. CPT Week, April 2001Darin Acosta14 Prototype Peripheral Crate Backplane

15. CPT Week, April 2001Darin Acosta15 Schedule & Plans The merged Sector Receiver/Sector Processor concept looks feasible and saves latency è Approximately 5.5 BX savings so far, work continuing è All R&D successful: p New optical links, new synch SRAM, SP-on-a-chip, GTLP backplane Single crate Track-Finder is simpler to maintain Proposal is to develop a new prototype by late summer 2002 è Possible use for integration tests with DT Track-Finder? è Possible use for structured beam tests? è Need to define a DAQ interface for readout è Slow control monitoring is presumably through VME