1. http://www.eet.bme.hu Budapest University of Technology and Economics Department of Electron Devices Integrated circuits, IC design Overview, main features, design & manufacturing, costs, etc. http://www.eet.bme.hu/~poppe/miel/en/16-ICdesign1.pptx

2. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 2 Once more about the development trends ► Moore's law and its manifestations ► Roadmap data

3. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 3 Recap ► We've seen what building blocks are being used in today's digital ICs:  CMOS logic gates main features, construction –logic model → circuit schematic ► We've seen the basic principles of IC manufacturing  planar process, photo lithography ► We've seen that the in-depths structure is determined by 2D shapes on the applied photomasks: layout ► We've seen that there was a direct path from the logic level circuit schematics to the layout ► Now we discuss some non technical aspects of IC manufacturing

4. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 4 Microelectronics: fastest growing industry Moore's law ► In 1965 Gordon Moore predicted that in every 14..18 months the number of transistors integrated in a chip will double (exponential growth) ► This prediction is valid even today. ► The 1 million transistors/chip threshold was reached in the 1980-ies  2300 transistors, 1 MHz clock frequency (Intel 4040) - 1971  16 millió transistors (Ultra Sparc III)  42 millió transistors, 2 GHz clock frequency (Intel P4) - 2001  140 millió transistors, (HP PA-8500) ► More than Moore: further increase of integration density, e.g. 3D stacking of chips (RAM-s, pen drives)

5. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 5 Technology trends: SIA roadmap ► Leading industrial experts provide continousely updated forecasts about the development trends microelectronics (manufacturing processes and technologies) http://www.itrs.net/ntrs/publntrs.nsf Year199920022005200820112014 Feature size (nm)180130100705035 Mtrans/cm 2 714-2647115284701 Chip size (mm 2 )170170-214235269308354 Signal pins/chip7681024 128014081472 Clock rate (MHz)6008001100140018002200 Wiring levels6-77-88-999-1010 Power supply (V)1.81.51.20.90.6 High-perf power (W)90130160170174183 Battery power (W)1.42.02.42.02.22.4 NTRS = National Technolgy Roadmap for Semiconductors SIA = Semiconductor Industry Association Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm

6. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 6 Forecasts for the minimal feature size (MFS)

7. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 7 Supply voltage, threshold voltage and oxide thickness trends ► Physical limits approached Decrease of supply voltage, threshold voltage and oxide thickness with the decrease of the channel length

8. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 8 Increase of design productivity ► Increase of design productivity is behind increase of circuit complexity: 2003 19811983 19851987 1989 199119931995199719992001 2005 2007 2009 Logic Tr./Chip Tr./Staff Month. x x x x x x x 21%/Yr. compound Productivity growth rate x 58%/Yr. compounded Complexity growth rate 10,000 1,000 100 10 1 0.1 0.01 0.001 Logic Transistor per Chip (M) 0.01 0.1 1 10 100 1,000 10,000 100,000 Productivity (K) Trans./Staff - Mo. Complexity

9. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 9 Some global issues of IC design and manufacturing ► Increasing complexity / increasing costs ► Gap between complexity and design capacity ► Design and manufacturing separated ► Cost reduction

10. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 10 Challenges in Digital Design ► Microscopic Problems  Ultra-high speed design  Interconnect  Noise, Crosstalk  Reliability, Manufacturability  Power Dissipation  Clock distribution ► Macroscopic Issues  time-to-market  design complexity (millions of logic gates)  high abstraction level, testing  reusability, IP, portability  systems on a chip (SoC)  tool interoperability YEARTech. (MFS, μm) ComplexityClock frequency Design effort in person years Design cost 19970.3513 M Tr.400 MHz210$90 M 19980.2520 M Tr.500 MHz270$120 M 19990.1832 M Tr.600 MHz360$160 M 20020.13130 M Tr.800 MHz800$360 M

11. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 11 Global characteristics of a design ► Functionality ► Costs  One-time, fix costs or non-recurring engineering costs (NRE) – e.g. labor cost of design  proportional costs (RE) – materials, packaging, testing ► Reliability, robustness  noise margins  noise immunity ► Performance  speed (delays)  dissipation (energy consumption) ► Time-to-market

12. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 12 Manufacturing costs of ICs ► One-time, fix costs or non-recurring engineering costs (NRE)  Costs of the design personal effort / labor cost of design work, CAD framework license fee labor costs of design verification mask manufacturing cost  Determined by the design complexity and design productivity  More significant in case of smaller production volumes ► Recurring engineering costs  costs of silicon processing proportional to the chip area  assembly costs (bonding, packaging)  testing cost per IC = proprtional costs per IC + fix cost volume Plus amortization costs of the foundry

13. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 13 Manufacturing costs of ICs ► Increasing NREs

14. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 14 Cost per Transistor 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 1982198519881991 1994 199720002003200620092012 cost: ¢-per-transistor Fabrication capital cost per transistor (Moore’s law)

15. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 15 Proportional costs Si szelet (wafer) IC chip or die (AMD Athlon processors) ► Influenced by  wafer size, die size  yield: # of functional / # of manufactured ICs  testing in-line, before packaging final testing (after packaging)  assembly costs Going up to 12” (30cm)

16. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 16 Proportional costs (volume related) cost of a good die = costs of a wafer volume × yield die cost + die testing cost + assembly cost volume related cost = yield of final testing  is approximately 3

17. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 17 Numerical example for the yield ► Example  wafer diameter 12", die size 2.5 cm 2, 1 defect/cm 2,  = 3 (is a measure of process complezity)  252 dice/wafer(rounded wafer, rectangular dice!)  die yield: 16%  252 x 16% = only 40 dice / wafer ! ► Cost of a die is a strong function of die size (area)  proportional to the 3 rd or 4 th power of the size

18. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 18 Examples for chip cost price ChipInter- connect layers MFSWafer cost defects / cm 2 Area (mm 2 ) chip / wafer yieldChip cost 386DX20.90$9001.04336071%$4 486DX230.80$12001.08118154%$12 PowerPC 601 40.80$17001.312111528%$53 HP PA 7100 30.80$13001.01966627%$73 DEC Alpha30.70$15001.22345319%$149 Super SPARC 30.70$17001.62564813%$272 Pentium30.80$15001.5296409%$417

19. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 19 Increase of design productivity ► Increase of design productivity is behind increase of circuit complexity: 2003 19811983 19851987 1989 199119931995199719992001 2005 2007 2009 Logic Tr./Chip Tr./Staff Month. x x x x x x x 21%/Yr. compound Productivity growth rate x 58%/Yr. compounded Complexity growth rate 10,000 1,000 100 10 1 0.1 0.01 0.001 Logic Transistor per Chip (M) 0.01 0.1 1 10 100 1,000 10,000 100,000 Productivity (K) Trans./Staff - Mo. Complexity Possible solutions: 1.DESIGN ON HIGHER ABSTRACTION LEVEL 2.AUTOMATED PHYSICAL DESIGN (SYNTHESIS)

20. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 20 Manufacturing and design Vertical structure: from the manufacturing process Horizontal structure: from the design These are separated in space and time The link between the design and manufacturing is established by the design rules. This applies to the (lateral) geometry of the devices. Regarding the operation of the active devices the link between the technology and design is realized by the model parameters which are used in computer simulation (e.g. SPICE simulations).

21. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 21 Manufacturing and design ► Manufacturing plants (fabs) are more and more expensive  Order of magnitude of billion US $ (huge CapEx costs)  Less and less advanced fabs world-wide ► Using the processes is getting also more expensive  Due to costs of masks, NRE (non-recurring engineering cost) of the advanced IC-s is increasing ► Few fabs – many designers  waferless fab – e.g. Silicon Labs, Duolog Design and manufcaturing are strictly separated, but for proper design one has to be aware of the basics of the manufacturing processes and the physical operation of the devices.

22. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 22 Ways of reducing costs ► Pre-design  Example: standard cell design (see details later) Essentially: We work with pre-design circuit elements (both in terms of schematics and layout). ► Pre-fabrication (see also pre-fab buildings)  Extreme example of the pre-fab principle for digital circuits: FPGA (Altera, Xilinx) FPGA = field programmable gate array It’s a matrix of logic gates with user programmable interconnections Includes everything which is needed for a digital circuit. The NRE of manufacturing is distributed over among a huge number of manufactured IC-s. Costs of individual circuit design are only the cost of preparing a HDL description of the circuit. Most popular realization technique today.

23. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 23 Ways of reducing costs ► MPW – multi-project wafer  One wafer – joint manufacturing of multiple designs: tipycally 10-20 designs on the same wafer  Individual design  Individual fabrication  costs (NRE-s): 10-20 fold reduction per design  prototyping / small volume production See details later

24. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 24 Overview of IC design EDA framworks ► Abstraction levels ► Typical tools ► Design using HDL – see the lab sessions

25. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 25 Optimization Physical device simulationProcess simulation Device parameters Design rules Behavioral description Specification in VHDL or in Verilog System simulator System level design Structural description Schematic editor Logic simulation Synthesis Logic level design Layout generation Layout description Layout editorCircuit simulator Timing parameters Transistor level design Abstraction levelRepresentation: Simulator: CAD tools in VLSI design Process and device design: TCAD tools used in silicon foundries. Ordinary designers do not use such tools.

26. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 26 CAD tools in VLSI design ► Circuit entry  Textual: using hardware description languages or HDLs (e.g.: Verilog, VHDL) behavioral description (Verilog, VHDL, SystemC) structural description (Verilog, VHDL)  Graphical: schematic entry (structural description) ► Simulation (on all abstraction levels)  system level, gate level logic, transistor/circuit  results visualization tools  tools for conceptual design, physical design verification tools ► High level synthesis: behavioral → RTL → structural ► Layout synthesis On all abstraction levels a given representations of the design – data bases

27. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 27 CAD tools in VLSI design

28. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 28 CAD tools in VLSI design

29. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 29 Circuit entry using an HDL ► Formerly: different in-house HDLs  exchange / re-use of designs  standards were needed VHDL(Very high speed IC Hardware Description Language): defined by the US DoD (Department of Defence); became the IEEE standard ► Suitable to describe all kinds of electronics systems realized by all kinds of technology ► Abstraction levels where VHDL can be used  Behavioral: for the description of the algorithm  Register Transfer Level, RTL: for the description of the data flow  Structural: logic gate level description

30. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 30 Main features of VHDL ► Technology independent description ► Generic language: on structural level description is independent of the characteristics of the assumed elementary building blocks ► Human readable, relatively easy to read ► entity and architecture blocks  entity: declaration of the name, inputs and outputs and further parameters of the building block  architecture: description of the operation and some actual physical parameters within this: the "instructions" between the begin & end keywords are "executed" at the same time (hardware!)

31. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 31 Verilog, SystemC ► Verilog: an HDL originating from the C language  "The" language in the CADENCE design environment  Simple, easy to read, most EDA environments can handle ► SYSTEM C: a new HDL based on C++  the usual language of hardware-software co-design  in fact collection of appropriate C++ classes Synthesis options e.g: 1.SystemC  Verilog converter 2.Verilog  VHDL converter 3. VHDL based synthesis tool

32. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 32 Simple example VHDL Verilog Using Verilog is dealt with in the lab

33. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 33 Hardware design with HDL ► Like computer programming ► BUT: the result will be a real hardware E.g. a for (i=0, i<n, i++) like loop means, that the building blocks referred to in the core of the loop must be "placed" (or instanced) n-times, e.g. connection to an n-bit bus ► In case of a circuit block designed with HDL we do not know yet what will be the final realization technology. ► The result of technology mapping could be:  netlist of a full custom IC (base of layout synthesis)  FPGA (generating a code to be downloaded int an FPGA) Discussed during lab sessions in details

34. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 34 Some professional IC design tools ► Mentor Graphics: some of Mentor's tools are used in the lab ► Cadence: Using this suite we demonstrate a complete IC designflow ► Usual platforms (Linux, Windows)

35. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 35 E.g.: MPW design & manufacturing ► Players:  silicon foundry (e.g. ST, AMS, NXP,...)  EDA vendor (pl. Cadence, Mentor,...)  Packaging house  MPW service provider - silicon broker (pl. EUROPRACTICE, CMP, MOSIS)  end-user who is also the designer is (like us) ► MPW manufacturing = Multi-Project Wafer  1 Si wafer: 10-15 chips,  manufacturing runs: every 2-3 months (3-4-5 times a year)  turnaround: from layout submission to packaged chip: 2-3 months  sharing the costs (NREs), costs proportional to Si-area E.g.: 250 EUR/mm 2, 4 mm 2  1000 EUR + 100 EUR packaging 5 packaged chips, 10 bare dice (66 EUR/chip)  typical use case: prototyping  small volume production: pl. 5-6 wafers with the same chip

36. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 36 E.g.: MPW design & manufacturing MPW service provider designer 3 designer 2 designer 1

37. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 37 E.g.: MPW design & manufacturing MPW service provider Designer and end-user Si-foundry Packaging house EDA vendor CAD tool CAD tool, design kit Design rules, device parameters, standard cell library Chip layout Chip layouts united Si wafer with 10-15 ICs Bare chips Packaged IC Packaged ICs

38. Budapest University of Technology and Economics Department of Electron Devices 20-11-2014 Integrated circuits, IC design © András Poppe, BME-EET 2008-2014 38 E.g.: MPW design & manufacturing