1. Tom McMullen Week 6 11/3/2013 – 15/3/2013

2. LETI wafer thinning project flow Phase 1 IDProject NameOwnerDaysStartEnd 3-Feb10-Feb17-Feb24-Feb3-Mar10-Mar17-Mar24-Mar31-Mar5-Apr12-Apr19-Apr26-Apr 1.0Thin Wafer AssembliesT. McMullen01-Feb30-Sep Week 1Week 2Week 3Week 4Week 5Week 6Week 7Week 8Week 9 1.1 PHASE 1 - Layout and mask production, first 2 wafers with microbumps delivered to AdvacamLETI - 3D101-Feb29-Mar LETI accpets CERN proposal 1.1.1Send gds to LETIT. McMullen51-Feb8-Feb 1.1.2 Send 2 FEI4b wafers to LETIR. Bates51-Feb6-Feb 1.1.3 Confirm step size on wafer and centre ofset variation on waferLETI51-Feb6-Feb 1.1.4 Layout and mask productionLETI101-Feb11-Feb Deliverable 1: Microbumb gds files 1.1.4 First 2 wafers with micro bumps delivered to AdvacamLETI4912-Feb2-Apr Deliverable 2: First 2 wafers with micro bumps delivered to Advacam Current Deliverable Target not met

3. Action List Phase 1 and 2 ActionWhatWhoWhenComment 6Further funding for flip-chip processRbates\Cbuttar31/3/2013Richard has confirmed this is all in place 7Bow measurement set-upTMcM31/2/2013 Contacted SMC to arrange one day set-up. Tool is down at the moment 8Sensors for flip chippingAll31/3/2013Sensor availablilty for flip-chip process - Meeting rqd 9Assembly probe test solutionTMcM19/3/2013Pobe test solution for flip-chipped assemblies - yield maps 10FEI4B probe card and probe set-upRbates/TMcM19/3/2013FEI4B test solution for assembly testing yeild maps 11Experience with FEI4A probe card set-upRbates/TMcM19/3/2013 FEI4A probe card set-up and testing of assemblies on Wentworth

4. Highlights and issues  Bump gds design completed and mask delivery due end of next week LETI are confident they will have delivered wafers to ADVACAM by deliverable date.  Meeting required to discuss sensor availability for the flip-chip process Amount of sensors for flip-chipping – good statistical analysis required for micro-bump yield – Richard and I have begun discussions on this. IBL TDR bump spec: ○ Pitch = 50um ○ Bump density = 26,880 per ROIC ○ Defect rate <0.0004 ○ ROIC thickness <200um FEI4b Assembly testing ○ FEI4b probe card required ○ Test equipment/apparatus required ○ Semi-auto testing solution required for assemblies  Two wafers shipped to LETI for technology run 2  SMC FSM thermal cycling tool is out of use at the moment. I have given them dates for when the tool is needed and asked for assurance that the tool will be ready by this time  Masks delivered to LETI and fist 2 wafers for flip-chip with micr- pillars should be available on time.

5. Wafer Inventory Wafer #Wafer IDYieldPurposeComment 1VMB8WDHG= 34, y=17, R=8, B=1Full thickness micro-bump testDelivered to LETI. High-yielding die. Micro-bump yeild testing on assemblies 2V6B8WUHG= 43, y=13, R=4, B=0Full thickness micro-bump testDelivered to LETI. High-yielding die. Micro-bump yeild testing on assemblies 3VUAYCRH First technology run. Run 2 Received at Glasgow Wafer thinning to 100microns. Used for thermal cycling bow measurements at SMC. Ship to LETI. Shipped to LETI 4ABPJXGH First technology run. Run 2 Received at Glasgow Wafer thinning to 100microns. Used for thermal cycling bow measurements at SMC. Ship to LETI. Shipped to LETI 5 Second technology run. Run 3Wafer to be identified and delivered to glasgow 6 Second technology run. Run 3Wafer to be identified and delivered to glasgow 7 Third technology run. Run 4Wafer to be identified and delivered to glasgow 8 Third technology run. Run 4Wafer to be identified and delivered to glasgow 9 Forth technology run. Run 5Wafer to be identified and delivered to glasgow 10 Forth technology run. Run 5Wafer to be identified and delivered to glasgow

6. Design proposal - Microbumps schape : round shape (32 sides) instead of octogon - Electrical Continuity test proposed -Sacrified dies for alignment Bottom right corner Bottom left corner Proposed tests structures : -Only on 2 alignment chips - 2 Microbumps with 50µm diameter on each metal pad  2 pads on bottom left & 2 pads on bottom right -Test will be done directly on microbumps with microtips Proposed tests structures : -B – pad array will be use for continuity checks for contact between Cu pillars and aluminium pads. This will not affect the functionality of the chip.

7. LETI wafer thinning project flow Phase 2