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OS Implementation On SOPC Final Presentation

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1 OS Implementation On SOPC Final Presentation
Performed by: Ariel Morali Nadav Malki Supervised by: Ina Rivkin

2 Project Goals Assemble a SOPC system, using Nios II processor on Altera’s DE2 board, based on Cyclone II FPGA. Implement Micrium’s µC OS-II. Build a system that includes VGA, Keyboard and Ethernet , demonstrating µC OS-II abilities.

3 Project Scheme

4 The System The SOPC includes: Nios II Processor
Internal and external memory (onchip & sdram) PS/2 Keyboard VGA UART PLL PIOs (Seven-Segments & LEDs)

5 Micrium’s µC OS-II Mainly for embedded systems Main features:
Scalable (5-24KB) Real time Pre-emptive multitasking Priority based Limited (but big enough) number of tasks Supply OS services: Semaphores and mutexes Message mailboxes and queues Timer and memory management

6 Micrium’s µC OS-II µC OS supports multi-tasking.
Each task is defined with the OSTaskCreateExt command. The arguments for this command are the task’s priority, pointers to the task’s function & stack, etc. After defining the tasks, the OS is initiated with the OSStart command, which has no arguments. The µC OS uses static priority in it’s scheduling. The available task with the highest priority always runs. In our software, we are using also the OSTimeDlyHMSM command. This command pauses a task for a defined period of time, allowing the other tasks to run.

7 The Software The software includes:
Micrium’s µC OS-II System Libraries Keyboard Driver VGA Driver Code that demonstrates µC capabilities: The code has two tasks running in parallel on the screen. Task #1: Gets input from the KB and prints it inside a window on the screen. Task #2: Prints a snake that moves randomly inside another window.

8 System Overview

9 Block Diagram The following diagram describes the System:

10 Quartos Screen Shot

11 SOPC Builder Screen Shot

12 Keyboard Serial access through the PS/2 Connector
Each time a key is pressed or released, data and control bits are transferred from the KB to the controller. An interrupt is sent to the processor in order to handle the information immediately. The controller saves up to 256 entries in a FIFO queue. Device drivers control and communicate with the PS/2 Core through two 32-bit registers. Communication with the PS/2 peripheral is done by writing or reading the registers through the Avalon Slave Port.

13 VGA The VGA core simplify the use of the VGA digital-to-analog converter (DAC) on the Altera DE2 board. The VGA Controller generates the timing signals required for the VGA DAC. It produces screen resolutions of 640x480 pixels for the DAC. The VGA DAC requires a 25MHz clock, supplied via the VGA_CLK pin. The VGA has two working modes – Pixel and Character modes.

14 Character Buffer The Character Buffer handles the conversion of characters to pixels, and sends them to the VGA Core. Each character occupies an 8x8 VGA pixel group. Therefore, resolution of 640x480 gives 80x60 characters. Each character location on the screen is identified by an x,y coordinate.

15 Other Peripherals SDRAM - Dynamic 8MB RAM, located on the DE2 board. Requires a 50MHz clock, shifted relatively to the CPU’s clock. PLL – receives a 50MHz clock, and generates the shifted clock for the SDRAM, and the 25MHz clock for the VGA DAC.

16 Ethernet Our original plan was to use the Ethernet in order to implement a web server. The DE2 board has a Davicom DM9000A Ethernet controller. In order to use TCP/IP protocol we planed to use the Nichestack TCP/IP stack. We learned that the DM9000A is not supported by the Nichestack.

17 Ethernet Efforts invested in order to use TCP/IP on the de2 board:
Successful implementation of Ethernet without TCP/IP (Sending and receiving raw packets) Study of the TCP/IP protocol Learn how to use and implement the Nichestack and its functions Unsuccessful Attempts to run Nichestack on the DE2 board - we found a group who wrote a special driver for the dm9000, which supposes to work with nichestack. after several attempts to use this driver, we came to the conclusion that it can’t be done in a reasonable amount of time.

18 Main Difficulties The µC didn’t work with the basic (economical) Nios II Processor. We had to use the more advanced processor. The on-chip memory was not sufficient for our software. We added the SDRAM memory. We learned that the SDRAM requires a shifted clock. We used the PLL to provide this clock. A lot of time and effort was invested in the attempt to implement TCP/IP on the DE2 board.

19 Planning for Project B Use of PCIE board that includes an ethernet controller supported by nichestack. Implementation of a web server using nichestack. The server will be managed and configured using Telnet protocol. Internet HTTP Telnet

20 Thank You

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