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1 4446 Design of Microprocessor-Based Systems Dr. Esam Al_Qaralleh CE Department Princess Sumaya University for Technology Serial Interface.

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Presentation on theme: "1 4446 Design of Microprocessor-Based Systems Dr. Esam Al_Qaralleh CE Department Princess Sumaya University for Technology Serial Interface."— Presentation transcript:

1 Design of Microprocessor-Based Systems Dr. Esam Al_Qaralleh CE Department Princess Sumaya University for Technology Serial Interface

2 11-2 External Interface Two ways of interfacing I/O devices –Serial Cheaper Slower –Parallel Faster Data skew Limited to small distances

3 11-3 External Interface (contd) Two basic modes of data transmission

4 11-4 External Interface (contd) Serial transmission –Asynchronous Each byte is encoded for transmission –Start and stop bits No need for sender and receiver synchronization –Synchronous Sender and receiver must synchronize –Done in hardware using phase locked loops (PLLs) Block of data can be sent More efficient –Less overhead than asynchronous transmission Expensive

5 11-5 External Interface (contd)

6 11-6 External Interface (contd) Asynchronous transmission

7 11-7 External Interface (contd) EIA-232 serial interface –Low-speed serial transmission –Adopted by Electronics Industry Association (EIA) Popularly known by its predecessor RS-232 –It uses a 9-pin connector DB-9 Uses 8 signals –Typically used to connect a modem to a computer

8 11-8 External Interface (contd) Transmission protocol uses three phases –Connection setup Computer A asserts DTE (Data Terminal Equipment) Ready –Transmits phone# via Transmit Data line (pin 2) Modem B alerts its computer via Ring Indicator (pin 9) –Computer B asserts DTE Ready (pin 4) –Modem B generates carrier and turns its DCE (Data Communication Equipment) Ready Modem A detects the carrier signal from modem B –Modem A alters its computer via Carrier Detect (pin 1) –Turns its DCE Ready –Data transmission Done by handshaking using –request-to-send (RTS) and clear-to-send (CTS) signals –Connection termination Done by deactivating RTS

9 11-9 Serial Data Transfer Asynchronous v.s. Synchronous Asynchronous transfer does not require clock signal. However, it transfers extra bits (start bits and stop bits) during data communication Synchronous transfer does not transfer extra bits. However, it requires clock signal Frame Start bit B0B1B2B3B4B5B6 Parity Stop bits Asynchronous Data transfer Synchronous Data transfer clk data B0B1B2B3B4B5 data Baud (Baud is # of bits transmitted/sec, including start, stop, data and parity).

10 USART Interface A7 A6 A5 A4 A3 A2 A1 IO/M D[7:0] RD WR A0C/D CLK TxC RxC TxD RxD 8251 RS232

11 11-11

12 11-12 Programming mode register Mode register Number of Stop bits 00: invalid 01: 1 bit 10: 1.5 bits 11: 2 bits Parity 0: odd 1: even Parity enable 0: disable 1: enable Character length 00: 5 bits 01: 6 bits 10: 7 bits 11: 8 bits Baud Rate 00: Syn. Mode 01: x1 clock 10: x16 clock 11: x64 clock

13 11-13 Programming command register EHIRRTSERSBRKRxEDTRTxE command register TxE:transmit enable DTR:data terminal ready, DTR pin will be low RxE:receiver enable SBPRK:send break character, TxD pin will be low ER:error reset RTS:request to send, CTS pin will be low IR:internal reset EH:enter hunt mode

14 11-14 Programming status register DSR SYNDE TFEOEPE TxEMPTY RxRDYTxRDY status register TxRDY:transmit ready RxRDY:receiver ready TxEMPTY:transmitter empty PE:parity error OE:overrun error FE:framing error SYNDET:sync. character detected DSR:data set ready

15 11-15 Simple Serial I/O Procedures Read start Check RxRDY Is it logic 1? Read data register* end Yes No * This clears RxRDY Write start Check TxRDY Is it logic 1? Write data register* end Yes No * This clears TxRDY

16 11-16 Errors –Parity error: Received data has wrong error -- transmission bit flip due to noise. –Framing error: Start and stop bits not in their proper places. This usually results if the receiver is receiving data at the incorrect baud rate. –Overrun error: Data has overrun the internal receiver FIFO buffer. Software is failing to read the data from the FIFO.


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