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A Temperature Sensor in 0.18µm CMOS with 62µW Power Consumption and a Range of ‑ 120..120°C Jan-Rutger Schrader Anne Stellinga Kofi Makinwa.

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Presentation on theme: "A Temperature Sensor in 0.18µm CMOS with 62µW Power Consumption and a Range of ‑ 120..120°C Jan-Rutger Schrader Anne Stellinga Kofi Makinwa."— Presentation transcript:

1 A Temperature Sensor in 0.18µm CMOS with 62µW Power Consumption and a Range of ‑ 120..120°C Jan-Rutger Schrader Anne Stellinga Kofi Makinwa

2 2 Contents 1. The Mars Seismometer Project 2. Temperature Sensor 1. Architecture 2. Detailed Implementation 3. Measurement Results

3 3

4 4 Seismometer Seismometer CAD view of broadband seismometer Test configuration

5 5 SHAMROC Readout Chip

6 6 5x5mm SHAMROC Readout Chip

7 7 Why a Temperature Sensor? Problem Temperature on Mars 0°C day Temperature on Mars 0°C day Electronics (self-heating): -55°C … 85°C Electronics (self-heating): -55°C … 85°C Required 24-bit SHAMROC ADC accuracy is 3ppm/°C Required 24-bit SHAMROC ADC accuracy is 3ppm/°CSolution On-chip temperature sensor measures die temperature On-chip temperature sensor measures die temperature ADC output values corrected using a (2 nd order) polynome ADC output values corrected using a (2 nd order) polynome

8 8 Specifications Temperature range:-120°C … 120°C Temperature range:-120°C … 120°C Resolution:0.06°C Resolution:0.06°C Non-linearity:±0.25°C Non-linearity:±0.25°C Conversion time:33ms Conversion time:33ms Power:62μW Power:62μW Supply voltage:3.3V analog, 1.8V digital Supply voltage:3.3V analog, 1.8V digital

9 9 Temperature Measurement Circuit: “Bipolar Core” (p=current ratio)

10 10 Block Schematic of Complete Temperature Sensor

11 11 Front-end and Timing 8C s Correlated Double Sampling

12 12 Opamp

13 13 Test Chip UMC 0.18μm RF CMOS

14 14 Chip Micrograph Active area: 0.29 mm²

15 15 Measured Error versus Reference Temperature Non-linearity ±0.25°C 3σ spread around ±0.3°C level

16 16 Measured Power Consumption

17 17 DARE vs Faraday digital library 2 tape-outs, same VHDL

18 18 Radiation Hardening Enclosed gate layout(leakage) Guard rings (latchup) IMEC DARE library

19 19 Radiation Tests 16kradNo parameter shifts (SHAMROC TID-requirements) 16kradNo parameter shifts (SHAMROC TID-requirements) 44kradOutput drift 0.75%Power unchanged 44kradOutput drift 0.75%Power unchanged 136kradOutput drift 6%Analog power in ON- state increased 136kradOutput drift 6%Analog power in ON- state increased 409kradChips stopped functioningLarge increase in analog & digital power 409kradChips stopped functioningLarge increase in analog & digital power No influence observed on IO-power. No influence observed on IO-power. DARE digital library: SEU-resistant logic. DARE digital library: SEU-resistant logic. Preliminary SEU test: only 1 possible single-event transient in multi-day test.

20 20 End


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