1. Slide: 1International Conference on Electronics, Circuits, and Systems 2010 Department of Electrical and Computer Engineering University of New Mexico Albuquerque, NM 87111 Ryan Helinski, Thomas LeBoeuf, Colby Hoffman, and Payman Zarkesh-Ha A Linear Digital VCO for Clock Data Recovery (CDR) Applications Department of Electrical & Computer Engineering

2. Slide: 2International Conference on Electronics, Circuits, and Systems 2010 Outline  Motivation  Basic Building Blocks  Clock-Data Recovery Circuit  Layout Design and Fabrication  Test and Measurement Results  Conclusion

3. Slide: 3International Conference on Electronics, Circuits, and Systems 2010 Motivation  Demands for multi-gigabit SerDes (e.g. gigabit Ethernet, PCI express, and hard disk drive Interface)  Lower V DD requires higher gain VCO, which results in higher noise sensitivity  Dual-control VCO for fine and course tunes becomes very attractive Output Frequency Dual-control VCO Fine Control Course Control Low gain High gain

4. Slide: 4International Conference on Electronics, Circuits, and Systems 2010 Ring-Oscillator-Based VCO  Pros  Easy to Implement in a Small Area  Robustness over Process and Temperature Range  Cons  Limited Control Voltage Range  Limit Output Swing  Highly Non-Linear Characteristics [Sidiropoulos’00]

5. Slide: 5International Conference on Electronics, Circuits, and Systems 2010 Basic Proposed Delay Element V DD CLCL V in V out I ref M1M2 M3M4 V in V out I ref t d = C L V DD 2I ref

6. Slide: 6International Conference on Electronics, Circuits, and Systems 2010 Detail CDR Circuit Diagram V DD CLCL V out M1M2 M3M4 M6 M7 V DD M8 V DD M9 V DD M5 V course V fine

7. Slide: 7International Conference on Electronics, Circuits, and Systems 2010 High-level Block Diagram of SerDes

8. Slide: 8International Conference on Electronics, Circuits, and Systems 2010 Detail Schematic of the Serializer  The serializer clock is generated internally with a gated ring oscillator  The input digital data (A_0 to A-7) is then serialized using a chain of shift register  The input send is used to trigger the send command

9. Slide: 9International Conference on Electronics, Circuits, and Systems 2010 Serializer Layout

10. Slide: 10International Conference on Electronics, Circuits, and Systems 2010 Detail Schematic of the Deserializer  The serializer clock is generated by the CDR circuit  The input serial data S_IN is then deserialized using chain of shift registers  The deserialization starts automatically once the start bit is detected.

11. Slide: 11International Conference on Electronics, Circuits, and Systems 2010 Deserializer Layout

12. Slide: 12International Conference on Electronics, Circuits, and Systems 2010 Clock and Data Recovery (CDR) Circuit  The CDR circuit consists of Hogge phase detector, 2) Charge pump and loop filter, and 3) the proposed voltage controlled oscillator

13. Slide: 13International Conference on Electronics, Circuits, and Systems 2010 Clock and Data Recovery (CDR) Layout

14. Slide: 14International Conference on Electronics, Circuits, and Systems 2010 LVDS Transmitter and Receiver  Better noise control and lower power consumption is provided by low-voltage differential signaling (LVDS)

15. Slide: 15International Conference on Electronics, Circuits, and Systems 2010 LVDS Transmitter and Receiver Layout

16. Slide: 16International Conference on Electronics, Circuits, and Systems 2010 The SerDes Testchip Layout Photograph  Chip size = 1.5mm x 1.5mm

17. Slide: 17International Conference on Electronics, Circuits, and Systems 2010 The VCO Specifications  MOSIS 0.5um ON Semiconductor CMOS Process  VCO center frequency of 89 MHz  VCO gain of 6MHz/V  VCO frequency range from 81MHz to 100MHz

18. Slide: 18International Conference on Electronics, Circuits, and Systems 2010 VCO Frequency versus Control Voltage

19. Slide: 19International Conference on Electronics, Circuits, and Systems 2010 SerDes BER Characteristics

20. Slide: 20International Conference on Electronics, Circuits, and Systems 2010 SerDes Test Waveforms at 90MHz  Test patterns: 0x5C and 0x11  Successful transmission  Transmission length 10.23 feet  Lock frequency of 90 MHz  LVDS voltage of 3.705V

21. Slide: 21International Conference on Electronics, Circuits, and Systems 2010 SerDes Characterization Summary

22. Slide: 22International Conference on Electronics, Circuits, and Systems 2010 Conclusion  A linear dual control VCO circuit was proposed.  To prove the concept a testchip of SerDes was demonstrated using the proposed CDR concept.  The testchip was manufactured using 0.5um ON semiconductor through MOSIS.  The measurements demonstrate that the CDR concept is practical and can be scalable to higher frequency ranges.

23. Slide: 23International Conference on Electronics, Circuits, and Systems 2010 Acknowledgement  The support of educational MOSIS program to manufacture the chip is greatly appreciated.