1. Synthesizer Tutorial V. S. Reinhardt Page 1 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Frequency and Time Synthesis A Tutorial Victor S. Reinhardt June 6, 2000

2. Synthesizer Tutorial V. S. Reinhardt Page 2 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Frequency and Time Synthesis Tutorial Organization Basic Concepts –What is a Synthesizer? –Basic Concepts of Frequency and Time Synthesis Direct Analog Synthesis –Analog Building Blocks –(Digital Building Blocks used to Generate Frequencies) –No VCO’s Indirect Synthesis –Uses Phase or Frequency Locked VCOs Direct Digital Synthesis –Uses Digital Processing Techniques to Generate Output –Digital Circuits used to Process Numbers –No VCO’s

3. Synthesizer Tutorial V. S. Reinhardt Page 3 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Synthesizer One or More Reference Sources Output f o f r1 f rN...... Basic Concepts What is a Synthesizer? One or More Input Reference Sources f r1 …f rn Translation to New Frequency f o Phase or Frequency Coherent With References Basic Properties –Frequency Range –Frequency Resolution –Switching Rate/Settling Time –DC Power, Weight, Cost, etc. –Phase/Frequency Stability (Time Domain, Environmental Effects) –Spectral Purity (Frequency Domain, Spurs, Noise)

4. Synthesizer Tutorial V. S. Reinhardt Page 4 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Ideal Periodic Waveform Periodic Function F(  V = A F(  )  = Phase of Function F(  2  ) = F(  ) In Time Domain   =  o t  o  =  Angular Frequency  o  = 2  f o f o = 1/T o = Frequency  not a True Observable –Measurement Depends on Inverting F(  ) –Must Keep Track of Number of Cycles for Multiples of 2  –Best Determined at Zero Crossings where Slope Large Amplitude A Positive Zero Crossings at t n =nT o  n =2  n tt Amplitude A tt Period T o  =2  V V Sine Wave Pulse

5. Synthesizer Tutorial V. S. Reinhardt Page 5 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Non-Ideal Waveform Amplitude and Frequency Now Function of Time Angular Frequency Error   = d  /dt Frequency Error  f  f =  Fractional Frequency Error y y =   =  f/f o y = (d  /dt)   t V Zero Crossing Variation Time or Phase Error Peak Variation Amplitude Error Force Nearly-Periodic Waveform into Periodic Form V = ( A + a(t) )·F[  o t +  (t) ] a(t) Amplitude Error  (t) Phase Error

6. Synthesizer Tutorial V. S. Reinhardt Page 6 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Additive Noise and Phase & Time Error Additive Noise  V Generates Phase Error  t  =  V(t)/A –  in Radians Equivalent to Noise/Signal Ratio –dB(  ) Equivalent to dBc Time Error in Positive Zero Crossing  t = -   = -  V/(A   ) –Note Minus Sign –Positive  V Negative  t Positive  , t V For Sine Wave Near Zero V = A (  o t+  (t) ) VV  t For Non-Sine Wave: Effective A is Determined by Slope Near Zero Complex Representation VIVI A  VQVQ  V I =  V Q =  V

7. Synthesizer Tutorial V. S. Reinhardt Page 7 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Clock Reading vs Time Error A Basic Clock Contains a Frequency Reference and a Cycle Counter Zero Crossing Time Error  t = -   –Compares Equivalent Zero Crossings at Different Times Clock Reading Error x =   –Compares Cycle Counts or Normalized Phases at Same Time Note Thatx =  y dt But  t = -  y dt x tt Ideal Source fofo Frequency Reference Cycle Counter Basic Clock x

8. Synthesizer Tutorial V. S. Reinhardt Page 8 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Ideal Coherent Synthesizer Coherent Frequency Translation by Factor K –Multiplies the Input Frequency f r by a Factor K –Ideal: Doesn’t Add Noise Input Phase Error  r Also Multiplied by K –The Phase Error Integral of the Angular Frequency Error The y and x of a Reference Oscillator are Independent of the Final Output Frequency y o =  o oo K  r KrKr  r rr ===yryr x o = oo oo KrKr KrKr rr rr ===xrxr frfr Frequency Reference Ideal Coherent Synthesizer rr f o = Kf r  o = K  r

9. Synthesizer Tutorial V. S. Reinhardt Page 9 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Spectral Density Review A Random Variable u(t) is Wide Sense Stationary if the Autocorrelation Function R is only a Function of  R u (  ) = T -1  T u(t+  )u(t) dt The Spectral Density is the Fourier Transform of R u (  ) S u (f) =  e j2  ft R u (  ) d  For Frequency Translation K S  -output (f) = K 2 S  -input (f) S y-output (f) = S y-input (f) S x-output (f) = S x-input (f) S y (f) =  2 S x (f) S y (f) = S  (f) 22 22 y(t) = dx dt y(t) =  o -1 dd dt U(f) Filter H(f) V(f) = H(f)U(f) S v (f) = |H(f)| 2 S u (f) Important Property of S(f)

10. Synthesizer Tutorial V. S. Reinhardt Page 10 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Spurs in Time Domain Spurious Signal Rotates around Main Phasor at 2  f Time Domain Measurements are Sampled at Multiples of t n = nT o Generates Regular Pattern at Aliases of 1/  f  V o (t) Spur at  f o +  f Discrete Samples When Phasor Crosses Real Axis oo  f Phase Error Plot NoiseSpur Allan Variance   Counter Histogram x Phasor Diagram

11. Synthesizer Tutorial V. S. Reinhardt Page 11 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Direct Analog Synthesis Directly Generates f o Frequency without VCO Multiplicative Devices –Multipliers –Dividers –x Conserved Additive Devices –Mixers Others –Filters –Switches –Amps Also Add Their Own Noise f x N Nf Multipliers ÷ M f/Mf Dividers f1f1 f2f2 fnfn........ fofo Switches f a  f b fbfb fafa Mixers f a +f b +f c fbfb Filters Amplifiers  NN  /M xx  xx f in f out  xx

12. Synthesizer Tutorial V. S. Reinhardt Page 12 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Typical Direct Analog Synthesizer: Divide & Mix Two Parts of Synthesizer Switched Reference Section –Generates References 0, f r,…9f r –Switch Refs to LO’s f 1, f 2,, f 3 … Divide and Mix Section (3 Stages Shown) –Divide f 3 =N 3 f r by 10 –Mix with f 2 =N 2 f r and Filter to Produce f 2 +f 3 /10 (Bypass Mixer if N 2 =0) –Repeat Divide, Mix, and Filter with f 3 =N 3 f r End Result f o = [N 1 + N 2 /10+N 3 /100 + …]f r –Each N Selects Digit of Output + 10 f 3 =N 3 f r f 3 /10 f 2 =N 2 f r f 2 +f 3 /10 f 1 =N 1 f r + 10 f o = f 1 + f 2 /10+f 3 /100 frfr Reference Generator frfr 2f r 9f r... Switch Matrix f1f1 f2f2 f3f3... f k =N k f r (N k = 0 to 9)

13. Synthesizer Tutorial V. S. Reinhardt Page 13 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Component Design Parameters General Parameters –Frequency Response –Speed (Switches) –DC Power –Cost, Weight, & Size Phase Noise (See Left) Phase Stability (Time, Environment) –Filters: Phase Shift over Temperature Critical Issue Spurs –Mixing IM’s –Switches: On/Of Loss Ratio Determines Spurs –Unwanted Multiplier Orders Phase Noise Characterization of Devices S(f) f 1/f Noise White Noise Floor 1/f Knee Cascaded Multipliers & Dividers xN 1 These Most Critical for S  (f) Make Lowest Noise and Highest N All x Contributions the Same Si 1-10 KHz GaAs, InP 0.1-1 MHz 1/f Knees ÷N 3 xN 2 ÷N 2 xN 3 ÷N 1

14. Synthesizer Tutorial V. S. Reinhardt Page 14 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Frequency Dividers (Counters) Asynchronous (Ripple) –Lowest Power –Most Phase Variation (Cascading Delays) –Can Use Clean-up Circuit Synchronous –High Power –Lowest Phase Variation Dual-Modulus –Almost Lowest Power –Low Phase Variation –Limit on Divide Number Regenerative & Analog Dividers –Can be Very Simple & Low Noise –Limited Frequency Range –Susceptible to Cycle Slips f in One Shot f out f’ out Clean-up Circuit... f in f out FF Synchronous Counter FF f in Asynchronous Counter... f out FF f in Delay  f out Regenerative Delay-  Divider R-S FF Q Reset Set

15. Synthesizer Tutorial V. S. Reinhardt Page 15 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Dual Modulus Counter –High Speed Dual Modulus (÷ P/P+1) Prescaler –2 Low Speed (÷M, ÷A) Counters –f out = f in /(MP+A)M  P, A = 0 to P-1 –Minimum Divide Ratio = P(P-1) Operation –Prescaler Starts with ÷(P+1) –Prescaler Switches to ÷P when A Count Reached –A and M Counters Reset when M Count Reached (Thus Must Have M  A) –Prescaler Switches Back to ÷(P+1) –For Contiguous Divide Numbers A = 0 to P-1 (so Must Have M  P-1) Dual Modulus Counter ÷ P/P+1 A Counter M Counter ÷A P/P+1 Control f in ÷ Out ÷M f out Reset

16. Synthesizer Tutorial V. S. Reinhardt Page 16 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Frequency Multipliers 1. Resistive Diode and Mixer –Broadband & Loss –Low Efficiency for High Harmonics 2. Step Recovery Diode & Varactor –Narrowband (to Match 5  Input Z) –Higher Efficiency for High Harmonics 3. Transistor –Highest Efficiency (Gain) –Too High Drive Can Cause Slow Damage from Avalanche Breakdown 2 & 3 Susceptible to Parametric Oscillations Nonlinear Device Filter fNf  Good Efficiency Limit Nf  1  Sharpness of Distortion Features (  ) Determine Amplitude of High Harmonics Device Degradation Due to Overdrive

17. Synthesizer Tutorial V. S. Reinhardt Page 17 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Mixers Many Types of Mixers –Single Device –Single, Double, Triple Balanced –SubHarmonic (Doubles LO Input) –Single Sideband Higher Order Mixers Suppress Spurious Mixing Products –f spur = Nf lO - Mf R –(N,M) = Spur Order Major Issue: Keeping Spurs Away From f IF f LO fRfR f IF Harmonics of f R Harmonics of f LO IF to Spur Ratios (dB) (WJ-M9E)

18. Synthesizer Tutorial V. S. Reinhardt Page 18 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Indirect Synthesis Utilizes Phase or Frequency Locked VCO to Act as: Operation Inverter –VCO Output f o Goes Through Frequency Translation T(f o ) –Phase or Frequency Discriminator Compares f r to T(f o ) and Generates Error Signal –Through Loop Filter and VCO Frequency Control, Error Signal Driven to Zero so f r = T(f o ) –Thus VCO Output is Inverse of T f o = T -1 (f r ) Tracking Filter –Uses Bandwidth Properties of Loop to Filter Reference Signal Loop Filter f o = Nxf r frfr ÷N f o /N VCO Example: Divider Loop Error Signal VCO Loop Filter Phase or Frequency Discriminator f o = T -1 (f r ) Freq Control Error Signal T(f o ) frfr Indirect Synthesis Frequency Translation

19. Synthesizer Tutorial V. S. Reinhardt Page 19 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Basic Phase Locked Loop Definitions –Open Loop Gain G(f) –Output Phase Error  –Reference Phase Error  r –VCO (Free Running) Phase Error  o Closed Loop Response H(f) =  /  r = G(f)/(s + G(f)) –H(f) has Low Pass Response with Knee at f n –1-H(f) has High Pass Response with Knee at f n Output Phase Error  = H(f)  r + (1-H(f))  o –Reference Characteristic f << f n –VCO Characteristic f >> f n V i =  r -   VCO rr  =  o - V o /s G(f) V o V i V o = G(f) V i 1-H(f) 1 f fnfn H(f) 1 f fnfn Idealized PLL

20. Synthesizer Tutorial V. S. Reinhardt Page 20 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Optimum Loop Bandwidth Free Running VCO: –Higher Near In Noise –Lower White Noise Floor Reference –Lower Near In Noise –Higher White Noise Floor Optimum Loop Bandwidth f n for Integrated Noise is Where Curves Cross May Have Other Reasons not to Choose this f n Such as Settling Time Requirement S  (f) f Free Running VCO S  (f) Reference S  (f) Optimum PLL S  (f) Optimum f n

21. Synthesizer Tutorial V. S. Reinhardt Page 21 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Oscillator Noise Characteristics Simple Oscillator Model Amp Noise S a (f) = (FkT/P in )·(1 + f f /f) Leeson’s Equation –Net Phase Around Loop = 0  R = -  a = -2Q L ·y –Note Resonator  R vs y slope Controls Oscillator Frequency –Thus Amp Phase Noise is Converted to Oscillator Frequency Noise S y (f) = 1/(2Q L ) 2 S a (f) –Since S y (f) = (f 2 /f o 2 )S  (f) We Obtain Leeson’s Equation S  (f) = (f o /(2Q L f)) 2 +1)(FkT/P in )(1+ f f /f) Gain = G a Noise Figure = F Flicker Knee = f f Noise Density = FkT Resonator Amp Oscillation Conditions |G a L| = Loop Gain > 1   Around Loop = 0 P in Near Resonance  R = -2Q L ·y Converted Noise + Original Amp Noise Loss = L Loaded Q = Q L

22. Synthesizer Tutorial V. S. Reinhardt Page 22 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Oscillator Noise Spectrum –S  (f) = K 3 /f 3 + K 2 /f 2 + K 1 /f + K 0 –Some Components May Mask Others Converted Noise –K 3 /f 3 and K 2 /f 2 –Varies with (f o /(2Q L ) 2 and FkT/P in Amp Noise –K 1 /f and K o –Only Function of FkT/P in S  (f) = (f o /(2Q L f)) 2 +1)(FkT/P in )(1+ f f /f) Oscillator Noise Spectrum Leeson’s Equation S  (f) f K 3 /f 3 K 2 /f 2 K 1 /f K0K0 QLQL Converted Noise Amp Noise

23. Synthesizer Tutorial V. S. Reinhardt Page 23 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Multiplied Oscillator vs Higher Oscillator Frequency Multiplied Oscillator –Whole Curve xN 2 –Higher Near-in Noise –Higher Far-out Noise Oscillator f o  Nf o –Only Converted Noise xN 2 (Same Q L ) –Higher Near-in Noise –Same Far-out Noise (Same FkT/P in ) This is Why Indirect Synthesis is Attractive –For Lower VCO Q L than Ref Q L Bump in Curve Oscillator at f o vs Nf o (Same Q L ) S  (f) N2N2 S  (f) = (Nf o /(2Q L f)) 2 +1)(FkT/P in )(1+ f f /f) fofo Nf o vs S  (f) f N2N2 S  (f) = N 2 (f o /(2Q L f)) 2 +1)(FkT/P in )(1+ f f /f) Multiplied Oscillator xN fofo Nf o N2N2

24. Synthesizer Tutorial V. S. Reinhardt Page 24 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Classification of Loops Loop Order (1st, 2nd, etc.) Phase vs Frequency Lock –PLL Lower Near in Phase Noise PLL: Loop Noise Converted to White Phase Noise FLL: Loop Noise Converted to White Frequency Noise –FLL Settles Faster Implementation –Analog Loops Analog Phase Discriminator Digital Phase Discriminator –Digital Loop (Filter) Phase/Frequency Error Quantization –Contininuous (or Near Continuous) –Bang-Bang (Sign of Error)

25. Synthesizer Tutorial V. S. Reinhardt Page 25 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. 1st & 2nd Order PLLs DC Open Loop Gain Set by  n (= 2  f n ) VCO Drift will Eventually Cause Loop to Unlock Doesn’t Completely Suppress Near-in VCO Noise (1/f 3 ) Fastest Settling Time for Same  n Injection Locked Oscillators equivalent to 1st Order PLL VCO rr 1st Order PLL  n = G s +  n H = nn DC Open Loop Gain Virtually Infinite VCO Drift No Problem Completely Suppresses Near-in VCO Noise (1/f 3 ) Slower Settling Time for Same  n VCO rr 2nd Order PLL s 2 +2s  n +  n 2 H = 2s  n +  n 2  = Damping Factor 1-H = s for s <<  n 1-H = s 2 for s <<  n

26. Synthesizer Tutorial V. S. Reinhardt Page 26 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Analog (Loop Filter) PLLs Phase Detectors –Mixers - Need Locking Circuit –Phase-Frequency Det. - Self-Locking –Loops with PFDs Also Called “Digital” Loops Divider Loop –Easy Lock –ASIC Implementation with PFD –Mixer & Loop Noise xN Multiplier Loop –False Lock & Spur Issues –Mixer & Loop Noise Not Multiplied –Sampling Phase Detector This Type Can Also Have Multiple Conversions (Mixers) fofo frfr ÷N f o /N Divider Loop VCO Analog Frequency Translation Analog Loop Filter Voltage Output Phase Detector frfr fofo fofo frfr xN f r xN Multiplier Loop

27. Synthesizer Tutorial V. S. Reinhardt Page 27 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Digital (Loop Filter) PLLs VCO Digital Loop Filter fofo f IF1 D/A Counters Analog Down- Conversions f c from VCO Digital Frequency Translations Averaging f IFk f r1 f rk... Can Lock to Many f r ’s: f r1... f rk –Weighted Averages, Separate Frequency Offsets, Error Correction Digital Phase Detection –Mix each f rk to Lower f IFk = K(f rk -K’f o ) –Counters Measure Zero Crossings t nk of f IFk with Resolution 1/ f c –Used to Calculate  IFk = K(  rk -K’  vco ) –Single Measurement Resolution  = 2  f IF /f c Must be < Ref Noise to Avoid Spurs Digital Loop Filter & D/A Control VCO –Loop Filter Sampled at Rate f IF –D/A LSB Must be < Ref Noise in Time 1/f IF to Avoid Spurs (Note: Frequency Resolution is Not Set by D/A LSB) T IF = 1/f IF T c = 1/f c  = 2  T c / T IF = 2  f IF / f c  IFk = 2  n - f IFk t nk ) t nk

28. Synthesizer Tutorial V. S. Reinhardt Page 28 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Example of Digital PLL D/A VCXO 10.23 MHz   Event Clock & PLL Processor Down- Converter AFS 1 13.4 MHz AFS’s Down- Converter 100 Hz f r1 AFS 2 f r2 f IF1 f IF2 fofo fofo VCXOAFS 180 KHz  76 3.53 KHz Cs 2.76 KHz Rb NN N= 3800 Cs N= 4858 Rb ~100 Hz 3.17 MHz 44 Downconverter  + -  Offset Compute Phase  + f Offset - Integrate  2nd Order Loop Filter x 2  n 98 ns Event Clock To D/A From D/C 10.23 MHz from VCXO Integrate x  n 2 /s Event Clock & PLL Processor (Reinhardt, 1999)

29. Synthesizer Tutorial V. S. Reinhardt Page 29 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Fast Settling Loop Techniques Pretune VCO Voltage –Approximate New Frequency Precharge Loop Integrator –Preset for New VCO Frequency Adaptive Loop Filter –Dynamically Adjust Bandwidth Reclock & Clear Divider –When Frequency Changes, Old Nozero State is Phase Error that Must be Slewed Out in PLL –Reclocking and Clearing Eliminates this Phase Slew Ping-Pong Switch & Second PLL –Presettle 2nd PLL before Switching fofo frfr ÷N Ping Pong Switch 2nd PLL Reclock & Clear Divider Pre- tune Adaptive Loop Filter Pre- Charge

30. Synthesizer Tutorial V. S. Reinhardt Page 30 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Effect of Precharge on Transient Response Precharge Pre-loads Integrator at Each New Frequency Command Generates More Ideal Stepped Frequency Response Loop TC = 0.1 s (Reinhardt, 1999)

31. Synthesizer Tutorial V. S. Reinhardt Page 31 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Cycle Slipping Becomes Problem at Low SNR within the Loop BW Phase Detectors are Periodic in Phase Finite Probability of Noise Burst Large Enough to Cause Slip to Next Cycle –Mean Time to Cycle Slip Exponential Function of 1/SNR in Loop BW Especially Problem with Sampling Phase Detectors (Kroupa, 1973) Energy  Mechanical Model of PLL with Noise Noise Burst Causes Cycle Slip Average Noise

32. Synthesizer Tutorial V. S. Reinhardt Page 32 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Post-Tuning Drift Post-Tuning Drift is Further Settling of VCO Frequency After Main Exponential –Can Last  s to Hours –Can Have Multiple time Constants Causes –Thermal Effects in Semiconductors –Surface Charging and Traps in Semiconductors –Bias Circuits and Regulators Problems/Issues –Varactor Tuner Prime Source –GaAs Devices are Especially Prone to Post-Tuning Drift –Semiconductor Effects are Very Lot Dependent VCO Frequuency Response to Voltage Step Post-Tuning Drift Single Exponential Equivalent Circuit of a Diffusion Process

33. Synthesizer Tutorial V. S. Reinhardt Page 33 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Direct Digital Synthesizers DDSs also called Numerically Controlled Oscillators Directly Synthesize a Selectable Output Frequency from a Clock Using Digital Techniques Types of DDSs –Pulse Output –Sine Output –Fractional Divider –Fractional Divider Phase Interpolation –Other

34. Synthesizer Tutorial V. S. Reinhardt Page 34 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Pulse Output DDS DDS is N-Bit Accumulator –For Each Clock Period 1/f c R in + K  R out in N-bit arithmetic –Can Write as Frac(r in + F)  r out –Fractional Frequency Word F = K/2 N –Fractional Register Value r = R/2 N Carry (or MSB) Output –On Average f o = F f c –RMS Jitter (No Output Filter) Period Jitter  T c /(12) 0.5 Phase Jitter   F/(3) 0.5 Example F=3/8, (T o =(8/3)T c ) –r = 0(C), 3/8, 6/8, 1/8(C), 4/8, 7/8, 2/8(C), 5/8, 0(C), ….. –Period Errors (  T/T o ): 1/3, 1/3, -2/3 N-Bit Register N-Bit Adder Clock Frequency Word K A B R out A+B “Square” Wave Out MSB R in Carry Pulse Out fofo Accumulator Used as DDS fcfc 123456789 Clock Cycles Carry R Timing Jitter Pulse Out TcTc

35. Synthesizer Tutorial V. S. Reinhardt Page 35 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. 0 -20 -40 -60 -80 0 0.20.40.60.81.0 Carrier f = 0.1225 Hz f = 1 Hz o c Frequency (Hz) Typical Pulse Output DDS Frequency Spectrum Large Spurs Very Close to Carrier Nature of Spurs Changes Drastically with fo Filtering Doesn’t Necessarily Reduce Phase Jitter (When Nearby Spurs Present) In General Closest Spur 2 -N fc

36. Synthesizer Tutorial V. S. Reinhardt Page 36 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Sine Output DDS Reduces Spurs by Adding Sine Table and DAC –N Determines Frequency Resolution –Argument of Sine Table = W Bits out of N Bit Accumulator –Sine Table Value = J Bits –DAC M Bits Nyquist Theorem: No (In- Band) Spurs if –Sine Table and DAC Perfect –f o < 0.5 f c (Must LP Filter Output) Spur Levels –6 dBc per bit for W & J –6-8 dBc per bit for M (Use Effective Number of Bits not Actual Bits) –Worst Case Determines Spurs Stepped DDS Output N-Bit Accumulator fcfc K Sine Table DACFilter W Bits M-Bits J-Bits fofo

37. Synthesizer Tutorial V. S. Reinhardt Page 37 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Typical Sine Output DDS Frequency Spectrums

38. Synthesizer Tutorial V. S. Reinhardt Page 38 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. High Speed DACs Spur Levels vs Speed dBc Output Frequency (MHz) (Essenwanger & Reinhardt, 1998)

39. Synthesizer Tutorial V. S. Reinhardt Page 39 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Sine Table Compression Algorithms Compression Algorithm ROM Req’ed Compression Ratio Logic Circuits Algorithm Error (dBc) None2 14 x121:1(none)-97.23 Cordic(none)N/A 14 pipelined stages 18 Bits Wide -84.25 Nicholas128:1adder/subtract -88.94 2 8 x9 2 8 x3 Raytheon Taylor Series 67:1 multiplier multiplexer, adder 13-bits ±1 LSB 2 5 x7 2 7 x14 2 7 x11 Modified Sunderland 2 8 x9 59:1adder-86.91 2 8 x4 Unmodified Sunderland 51:1adder 2 8 x11 2 8 x4 12-bits ±2 LSB Conventional Taylor Series 64:1 2 adders multiplier -97.04 2 7 x14 2 7 x9 2 5 x3 (*Modified from Essenwanger & Reinhardt, 1998) IIR Filter* (Presti, et. Al.) (none)N/A 3 pipelined stages Requires 1 calc of Sin  & Cos  per Freq No Limit

40. Synthesizer Tutorial V. S. Reinhardt Page 40 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Fractional Divider or Pulse Swallowing DDS Dual Modulus Prescaler –Normally ÷ n –Output Clocks Accumulator –On Accumulator Carry ÷ (n+1) Next Cycle N-Bit Accumulator R + K  R –Carry on Overflow Output on Prescaler –On Average f o = f c /(n+F) –RMS Jitter (No Output Filter) Period Jitter  T c /(12) 0.5 Phase Jitter   /(n+F)(3) 0.5 ) N-Bit Accumulator fcfc K Dual Modulus Prescaler ÷n/n+1 fofo Carry ÷n/n+1 Control Clock Cycles Carry R

41. Synthesizer Tutorial V. S. Reinhardt Page 41 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Phase Interpolation Fractional Divider (in PLL) Fractional Dividers Utilized Most Often in PLLs Can Reduce Phase Jitter by Utilizing R Value –At Carry rT c = Period Error –Utilize DAC & Linear Phase Detector to Correct for Error Represented by R Spur Levels Limited by –Linearity of Phase Detector –DAC Resolution Without Interpolation Can Reduce Spurs if 2 -N f c >>Loop Bandwidth N-Bit Accumulator K Divide by n/n+1 Control Carry Output Linear Phase Detector frfr DAC R Loop Amp VCO fofo

42. Synthesizer Tutorial V. S. Reinhardt Page 42 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. r-Space Spectrum 1357 Harmonics r-Space Frequency Spur Generation in DDSs Look-Up Table v(r) Quantized Sine Wave (Sine DDS) Square Wave (Pulse DDS) v(r) Periodic in r (Period=1) Discrete r-Space Harmonics Accumulator Samples v(r) at r n =f o t n v(f o t) Translates mth Harmonic to mf o Sampling at t n Causes Aliasing at f=mf o - m’f c Stepped Output Hold Function Stepping Adds Hold- Function Filter Spectrum of Hold Function Sinc 2 (  f/f c ) Output Spectrum 2f c fcfc 0 t-Space Sampled Spectrum 2f c fofo 1 3 5 7 1 7 5 3 0

43. Synthesizer Tutorial V. S. Reinhardt Page 43 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. DDS Spur Algebra Time Domain Properties of r n = Frac(nF) –Produces Periodic Sequence –In Irreducible form F can be Written as a/b (a and b Relatively Prime) –Time Domain Sequence Permutation of 0, 1/b, 2/b, …. (b-1)/b –So Period of Sequence bT c and Number of Unique Values b Frequency Domain Properties –Since Period bT c Sequence has Harmonic Exdpansion kf c /b = 0, f c /b, 2 f c /b, …. (b-1) f c /b,.... kf c /b = mf o - m’f c = [m(a/b) - m’]f c –Thus There are b Spurs from 0 to f c The Spur Spacing is f c /b There is a Large (Principal) Spur at f c -f o that is an Alias of the (Negative) Fundamental Frequency

44. Synthesizer Tutorial V. S. Reinhardt Page 44 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Converts Spurs to Broadband Spectrum fofo S  (f) Jitters Output at f o by   Jitters spur from mth Harmonic of v(r) by m   f spur f Spur Height Reduced Because of Larger Jitter Heuristic Explanation v(r) v(r + p) Fractional Frequency F N-Bit Accumulator r  Random Number Generator r + p p Destroying Coherence With Register Jitter Spurs Occur Because Uniformly Stepped Sequences Periodic –Introducing Jitter Destroys Periodicity –Jitter More Efficient with Spurs from High Harmonics of v(r) Expansion Converts Spur Energy to Broadband Phase Noise

45. Synthesizer Tutorial V. S. Reinhardt Page 45 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Wheatley Jitter Injection Used with Pulse Output DDS Destroys Spurs but Produces High Degree of Broadband Noise 0 -20 -40 -60 -80 0 0.20.40.60.81.0 Carrier f = 0.1225 Hz f = 1 Hz o c Frequency (Hz) 0 -20 -40 -60 -80 0 0.20.40.60.81.0 Carrier f = 0.1225 Hz f = 1 Hz o c Without Jitter InjectionWith Jitter Injection

46. Synthesizer Tutorial V. S. Reinhardt Page 46 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Randomized DAC DDS Experimental Results Used with Sine Output DDS Less Efficient at Reducing Spurs but with Lower Broadband Noise 5-Bit DAC No Jitter5-Bit DAC With Jitter11-Bit DAC No Jitter 0 -10 -20 -30 -40 -50 -60 -70 -90 -80 dBc f o =333.25 KHz f c =1 MHz Span=10 KHz RBW=10 Hz 0 -10 -20 -30 -40 -50 -60 -70 -90 -80 dBc (Reinhardt,1993)

47. Synthesizer Tutorial V. S. Reinhardt Page 47 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Frequency and Time Synthesis Final Summary The Basic Concepts Basic Outlined Here are Provide a Framework for Both the Design & Specification of Frequency and Time Synthesizers The 3 Types of Approaches Outlined Here Are –Analog Synthesis –Indirect Synthesis –Direct Digital Synthesis The Above Architectures Used in Combination are Often the Best Design Approach A List of References Follows