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HUGHES DDSSP1.PPT 5/24/93 VSR - Page 1 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on.

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Presentation on theme: "HUGHES DDSSP1.PPT 5/24/93 VSR - Page 1 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on."— Presentation transcript:

1 HUGHES DDSSP1.PPT 5/24/93 VSR - Page 1 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Spur Reduction Techniques in Direct Digital Synthesizers Introduction/Review of DDS’s Theory of Spur Generation Spur Reduction Techniques –Spurless Fractional Divider –Wheately Jitter Injection DDS –Randomized DAC DDS –Nonuniform Clock DDS –Nicholas & Samueli Technique (Will Not Be Discussed in Paper)

2 HUGHES DDSSP1.PPT 5/24/93 VSR - Page 2 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Direct Digital Synthesizers DDSs also called Numerically Controlled Oscillators Directly Synthesize a Selectable Output Frequency from a Clock Using Digital Techniques Types of DDSs –Pulse Output –Sine Output –Fractional Divider –Phase Interpolation –Other

3 HUGHES DDSSP1.PPT 5/24/93 VSR - Page 3 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Each Cycle R + K R Mod 2 N r + F o r Average Output Frequency: f o =F o f c Fractional Frequency Word: F o =K/2 N Fractional Register: Fract(r)=R/2 N Pulse Output DDS r  =2  r 22 0 44 66 Clock Cycles 01234567 Pulse Output N-Bit Accumulator (Register Value = R) Clock Frequency=f c Frequency Word K Carry=Pulse Output f o  r or  tt FoFo 1st Carry 2nd Carry 3rd Carry

4 HUGHES DDSSP1.PPT 5/24/93 VSR - Page 4 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Typical Pulse Output DDS Frequency Spectrum Large Spurs Very Close to Carrier Nature of Spurs Changes Drastically with F o Filtering Doesn’t Necessarily Reduce Phase Jitter

5 HUGHES DDSSP1.PPT 5/24/93 VSR - Page 5 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Sine Output DDS Stepped DDS Output Output Must be Filtered to Recover Pure Sine Wave N-Bit Accumulator Clock Freq=f c Frequency Word K Output f o Angle W Bits Sine Look-up Table M-Bit DAC Output J Bits

6 HUGHES DDSSP1.PPT 5/24/93 VSR - Page 6 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Typical Sine Output DDS Frequency Spectrum 5-Bit DAC11-Bit DAC 0 -10 -20 -30 -40 -50 -60 -70 -90 -80 dBc f o =333.25 KHz f c =1 MHz Span=10 KHz RBW=10 Hz

7 HUGHES DDSSP1.PPT 5/24/93 VSR - Page 7 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Fractional Divider or Pulse Swallowing DDS N-Bit Accumulator fcfc K fofo Divide by n/n+1 n/n+1 Control Carry Output Divider Normally  n Each Divide Cycle Clocks Accumulator R + K R Mod 2 N On Carry:  n+1 Next Divide Cycle On Average: f o = n + F o fcfc

8 HUGHES DDSSP1.PPT 5/24/93 VSR - Page 8 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Phase Interpolation DDS N-Bit Accumulator K Divide by n/n+1 n/n+1 Control Carry Output Linear Phase Detector fcfc DAC R Loop Amp VCO fofo

9 HUGHES DDSSP1.PPT 5/24/93 VSR - Page 9 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Spur Generation in DDSs Look-Up Table v(r) Quantized Sine Wave (Sine DDS) Square Wave (Pulse DDS) v(r) Periodic in r (Period=1) Discrete r-Space Harmonics Accumulator Samples v(r) at r n =f o t n v(f o t) Translates mth Harmonic to mf o Sampling at t n Causes Aliasing at f=mf o - m’f c Stepped Output Hold Function Stepping Adds Hold- Function Filter Spectrum of Hold Function Sinc 2 (  f/f c ) Output Spectrum 2f c fcfc fofo t-Space Sampled Spectrum 2f c fofo 1 3 5 7 1 7 5 3 fofo r-Space Spectrum 1357 Harmonics r-Space Frequency

10 HUGHES DDSSP1.PPT 5/24/93 VSR - Page 10 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Reducing Spurs in DDSs Spurs Occur Because Uniformly Stepped Sequences Periodic (Period = N’t c ) Destroying Periodicity or Uniformity will Reduce Spurs Spurless Fractional Divider Wheately Jitter Injection Randomized DAC DDS Nonuniform Clock DDS Nicholas & Samueli Technique Totally Random Output Jitter Injection Nonuniform Sampling Force K to be Odd Spur Reduction Techniques

11 HUGHES DDSSP1.PPT 5/24/93 VSR - Page 11 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Spurless Fractional Divider Divide by n/n+1 N-Bit Word Comparator n/n+1 Control Clock Period = t c Output Period = t o P n < K Random Number Generator PnPn K Each Output Clock Random N-Bit Word P n Generated P n = 0 to 2 N -1 If P n < K then Divide by n+1 F o = Probability that P n { "@context": "http://schema.org", "@type": "ImageObject", "contentUrl": "http://images.slideplayer.com/14/4212847/slides/slide_11.jpg", "name": "HUGHES DDSSP1.PPT 5/24/93 VSR - Page 11 Copyright 2005 Victor S.", "description": "Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Spurless Fractional Divider Divide by n/n+1 N-Bit Word Comparator n/n+1 Control Clock Period = t c Output Period = t o P n < K Random Number Generator PnPn K Each Output Clock Random N-Bit Word P n Generated P n = 0 to 2 N -1 If P n < K then Divide by n+1 F o = Probability that P n

12 HUGHES DDSSP1.PPT 5/24/93 VSR - Page 12 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Wheatley Jitter Injection DDS N-Bit Accumulator (Register Value = R) Clock Freq=f c Frequency Word K “Square” Wave Output f o N-Bit Adder Random Number Generator P n = 0 to K-1 F o =K/2 N R 22 Carry Adds Random P n to R Before Carry r Jittered from 0 to F o Equivalent to White Phase Jitter Washes Out Spurs Produces White Phase Noise

13 HUGHES DDSSP1.PPT 5/24/93 VSR - Page 13 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Wheatley Simulation Results Without Jitter InjectionWith Jitter Injection

14 HUGHES DDSSP1.PPT 5/24/93 VSR - Page 14 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Destroying Coherence With Register Jitter Register to Voltage Conversion v(r) v(r n + p n ) Fractional Frequency F o N-Bit Accumulator r n =Fract(nF o )  Random Number Generator r n + p n Produces Broadband Spectrum fofo S  (f) Jitters Output at f o by   Jitters spur from mth Harmonic of v(r) by m   f spur f Spur Height Reduced if Jitter Large Enough Heuristic Explanation pnpn

15 HUGHES DDSSP1.PPT 5/24/93 VSR - Page 15 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Randomized DAC DDS N-Bit Accumulator Clock Freq=f c Frequency Word K Output f o J-Bit Adder Random Number Generator k n = 0 to K’-1 R Sine Look-up Table Output J Bits M-Bit DAC K’=2 J-M Sine Output Embodiment Can be Inserted into Existing Sine Output DDSs Can Also be Used in Phase Interpolation DDS Washes Out Spurs Produces Much Lower Level of White Phase Noise

16 HUGHES DDSSP1.PPT 5/24/93 VSR - Page 16 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Randomized DAC DDS Experimental Results 5-Bit DAC No Jitter5-Bit DAC With Jitter11-Bit DAC No Jitter 0 -10 -20 -30 -40 -50 -60 -70 -90 -80 dBc f o =333.25 KHz f c =1 MHz Span=10 KHz RBW=10 Hz 0 -10 -20 -30 -40 -50 -60 -70 -90 -80 dBc

17 HUGHES DDSSP1.PPT 5/24/93 VSR - Page 17 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Nonuniform Clock DDS Pseudorandomly Non-uniform Clock Generator  R Calculator tt K  R=K  t N-Bit Accumulator Output Ping Pong Switch Sine Look-up Table DAC Odd/Even Buffers Odd Clock Even Clock Odd Clock DAC Even Clock  t varies Pseudorandomly from 0 to 2t c

18 HUGHES DDSSP1.PPT 5/24/93 VSR - Page 18 Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized. Conclusions Randomization Techniques are an Effective Way of Reducing Spurs Of Spur Reduction Methods Discussed –Jitter Injection Best Over-all Method –Produces Manageable Phase Noise –Minimimizes Added Complexity –Wheatley for Pulse Output –Randomized DAC for Sine Output & Phase Interpolation Can Make Up for Technology Limitations


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