1. Design Considerations for High Step-Down Ratio Buck Converters
4/17/2017
Design Considerations for High Step-Down Ratio Buck Converters
Ramesh Khanna – National Semiconductor, Richardson, TX
&
Satish Dhawan – Yale University, CT, USA

2. Buck converter
In Non-Synchronous buck converter Q2 is replaced with diode
Q1 on & Q2 off
Q1 off & Q2 on
DC gain

3. Continuous vs Discontinuous mode of Operation
4/17/2017
Continuous vs Discontinuous mode of Operation
When Q1 is turned on Input source charges the inductor and supplies the Output load
When Q1 turns-off Voltage across the inductor changes polarity and forward biases the sync diode, Q2 is allowed to turn-on. Energy stored in the inductor is supplies to the load. 3

4. Buck converter in Discontinuous mode

5. Specifications / Design considerations
4/17/2017
Specifications / Design considerations
Min
Max
Tolerance
Req'd
Vin
3.3 15
Vout
1.8
+/-3%
Output Ripple
50mV
Efficiency
85%
Transient
100A/usec
Ambient Temp
55C
Size
H x L x W
Enable x
Tracking
OV Protection
Current Limit
Cost Target
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6. Need for Efficiency Improvement
4/17/2017
Need for Efficiency Improvement
Efficiency Improvement is critical for any designs.
In order to maintain same heat dissipation improving efficiency from
85% to 91.9% doubles the output power.
Less issues with regards to thermal management
Improved reliability.
Output power delivered doubles from 40W to 80W for fixed power dissipation (loss) of 7W. If the converter efficiency increases from 85% to 92%
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7. Small Signal Model of Buck Converter
4/17/2017
Small Signal Model of Buck Converter
PWM Switch
dependent variable
dependent variable
independent variable
independent variable
Express dependent sources
and
as a function of
independent sources ,
and
duty cycle
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8. PWM switch model
Next step we perturb and linearize the equations, where we assume average voltage consists of constant “dc” component and small signal “ac” variation around the dc component.

9. PWM switch model
Combining the two sections, we have the small signal mode of PWM switch

10. Incorporating PWM switch in Buck Circuit
Small signal model of Buck converter - DC Analysis
For DC Analysis
L = Short circuit
C = Open circuit

11. Incorporating PWM switch in Buck Circuit
Small signal model of Buck converter – AC Analysis
For AC analysis we short the input source
Control to output is the most important transfer function as it is necessary for the design of stable feedback loop.

12. Incorporating PWM switch in Buck Circuit
Small signal model of Buck converter – AC Analysis Alternate Approach
For AC analysis we short the input source
Write differential equation for Voltage across inductor Lf
Write differential equation for Current thru the output capacitor Cf

13. Incorporating PWM switch in Buck Circuit
Write the two equations in matrix form
Solve matrix using cramers rule to obtain control to output transfer function.

14. MOSFET Selecton Model highlights the MOSFET critical parameters
4/17/2017
MOSFET Selecton
MOSFET – switching model
Model highlights the MOSFET critical parameters
Miller Capacitor
Junction capacitors of semiconductor devices are non-linear
At Vc there is twice the charge that a linear capacitor of value Co would have at Vo
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15. Critical MOSFET parameters
4/17/2017
Critical MOSFET parameters
Rg – MOSFET gate resistor along with gate driver resistance are extremely critical for high speed applications.
MOSFET gate resistance is temperature dependent thus increases with temperature - vendors provide curves Rdson vs temperature for better approximation.
Forward Transconductance and has units of (mho) Siemens
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16. Non-Linear junction capacitor in MOSFET
4/17/2017
Non-Linear junction capacitor in MOSFET
Miller Capacitor
Junction capacitors of semiconductor devices are non-linear
At Vc there is twice the charge that a linear capacitor of value Co would have at Vo
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17. MOSFET Switching Behavior : Turn-on
Turn-On Delay –
Input capacitor is charged from 0V to Vth.
Linear Operation
Vg increases from Vth to Miller Capacitor
Mosfet is carrying the entire Inductor current.
MOSFET Turn-On 4 stages
Reduce transition time during stage 2 to minimize switching losses
Critical Gate Drivers ability to source current
Vgs is Steady
Driver current diverted to discharge Cgd
Drain Voltage falls
4. Vgs increased from Vmiller to Vfinal
Mosfet fully enhanced
Cgs and Cgd charged
Rds_on reduced.

18. Mosfet Switching Behavior : Turn-Off
Turn-off Delay
Ciss is discharged from initial value to Miller Plateau.
Vds rises
Gate current is charging Cgd
Gate in its Miller Plateau
Mosfet in Linear mode
Vg falls from Miller to Vth
Cgs capacitor is started to discharged
MOSFET Turn-Off 4 stages
Reduce transition time during stage 3 to minimize switching losses
Critical Gate drivers ability to sink current.
4. Turn-off Stage
Vgs is further decreased with current coming out of Cgs capacitor.

19. Diode Reverse recovery
Current can flow from cathode to anode until diode turns off.
This can produce
High peak currents
High dissipation:
In the diode
In other circuit components

20. High Side Fet Losses Conduction and Switching Losses
Switch conduction losses
Switching losses during turn-on and turn-off
Driver losses
Capacitor drain-source losses
Reverse recovery losses

21. Low Side Losses
Profile of Loss in High side and Low side are quite different especially for Low output voltages.
Low side losses are dominated by conduction losses
High side conduction and switching losses
Select HS Mosfet for low Qg
Select LS Mosfet for low Rds_on

22. Mangetic Materials There are two classes of materials
1. Alloys of iron, which contain silicon (Si), Nickel (Ni), Chrome (Cr) and Cobolt (Co)
2. Ferrites – ceramic materials mixture of iron, Manganes (Mn), Zinc (Zn), Nickel (Ni) and Cobolt (Co)

23. Inductor Losses ( Conduction and Core)
DCR losses
Core losses
Core losses can be calculated based upon flux density, frequency of operation, core volume
Core vendors provide core loss data vs frequency used to estimate core losses
For Ferrite cores: Steinmetz equation defines core losses

24. Output Inductor saturation behavior
No Inductor Saturation
Waveform shows output inductor waveform in
normal operation
Inductor is saturated.
Saturation is reduction in inductance as function of current, which can destroy the MOSFET

25. Capacitor - Input / output
Input Capacitor selection criteria is to meet:
Input capacitor rms ripple current rating
Output Capacitor selection criteria is based upon
esr of the capacitor ( in order to meet o/p ripple voltage specification)
Bulk capacitance to ensure it meets maximum overshoot/ undershoot during transient conditions.
Ideal Capacitor
Real World Capacitor

26. Current Mode Control Current mode Control has two loops
Inner current loop
Outer voltage loop

27. Current mode control
Current loop stable for duty cycle less than 50% for Vin=12V Vout = 1.2V Duty cycle is 10%
Current loop un-stable for duty cycle greater than 50% - requires slope compensation

28. Adding slope compensation
For duty cycle > 0.5 slope compensation required.
Minimum slope required is ½ downslope of inductor current

29. Current loop Current loop is sampled data loop
Peak inductor current is sampled and held until next switchng cycle
Transfer function He models sampling nature of current loop

30. Buck Regulator with Current Mode Control
Shown on this slide is the same basic buck regulator power stage with the addition of the control circuitry. Control is accomplished though pulse width modulator of Q1. This particular control circuit is referred to current mode control. The main characteristic of current mode control is that the modulating ramp used by the PWM comparator is a signal derived from the buck switch current. When the buck switch is turned on, the current rises with the same profile as the inductor current.
Each period the modulation of Q1 is controlled as follows:
It can be seen that there are quite of steps that need to be accomplished each period. The minimum time required to complete these steps creates a minimum controllable on-time or duty cycle. For large step-down applications with a large Vin and much smaller Vout this minimum on-time can present a problem. The biggest challenge when designing for minimum on-time is the design of the current measure circuit. We’ll talk more about this in the following slides.

31. Why Emulated Current Mode?
Step down switching regulators designed for high input voltages must control very short minimum on-times to operate at high frequencies.
The maximum switching frequency (and size of the inductor and output capacitor) are function of the minimum on-time.
The on-time of conventional current mode controllers is limited by current measurement delays and the leading edge spike on the current sense signal. When the Buck FET turns on and the diode turns off, a large reverse recovery current flows, this current can trip the PWM comparator. Additional filtering and / or leading edge blanking is necessary to prevent premature tripping of the PWM. The emulated current signal is free of noise and turn-on spikes.
Leading edge spike, conventional current mode control.

32. Current Mode Control Advantages / Disadvantages
Current mode control is a single pole system. The current loop forces the inductor to act as constant current source.
Current mode control remains a single pole system regardless of conduction mode (continuous mode or discontinuous).
Inherent line feed-forward since the ramp slope is set by the line voltage.
By clamping the error signal, peak current limiting can be implemented.
Ability to current share multiple power converters.
DISADVANTAGES
Susceptibility to noise on the current signal is a very common problem, reducing the ability to process small on-times (large step-down ratios).
As the duty cycle approaches 50% current mode control exhibits sub-harmonic oscillations. A fixed slope ramp signal (slope compensation) is generally added to the current ramp signal.

33. Emulated Current Mode, How Does it Work?
Shown of this slide is the buck regulator power stage comprised of Q1, D1, L1 and Cout.
The objective is to create a signal that accurately represents the current through the buck switch Q1 without actually making a direct measurement.
When we study the characteristics of the buck switch current signal we can note that the signal can be broken down into two parts, a pedestal and a ramp. When the buck switch initially turns on the current level jumps to the same level that was conducting previously in the diode. By taking a sample-and-hold measurement of the diode current just before turning on the buck switch we can establish the pedestal level. A small current sense resistor is placed in series with the diode anode to accomplish this measurement.
Once the buck switch is turned on the characteristic of the ramping current is:
di/dt = (Vin – Vout) / L This is the basic inductor equation.
To emulate the ramping portion of the buck switch signal first we create a current source proportional to the difference between the input and the output voltage. If this current source flows into a capacitor, the ramping voltage across the capacitor will equal:
dv/dt = (Vin – Vout) / C
If we set the value of the capacitor proportional to the inductor value we can scale the capacitor voltage to match the ramping current signal.
The final step is to add the sample and hold diode current level to the capacitor ramp voltage. Now we have recreated the buck switch signal with no delays and no leading edge noise spike. We can now use this signal for pulse-width modulation and current limit purposes as in conventional CM control. Each period after the buck switch turns off the ramp capacitor is discharged in preparation for the next cycle.

34. Emulated Current Mode Waveforms
Emulated Current Mode Controller Timing
Sample and Hold
of Diode (Inductor)
Current
Shown on this slide is a timing diagram for the buck regulator power stage. You can see how the inductor current is the sum of the buck switch current and the diode currents. The sample and hold is accomplished at the times indicated by the yellow bars. This sample and hold establishes the pedestal level. Shown on the bottom is the emulated ramp signal scaled to 0.5 V/A.

35. Maximum Input Voltage vs Operating Frequency
For a minimum on-time capability of 80ns, the minimum duty cycle is therefore 80ns x Fsw. For low output voltage, high frequency applications the maximum switching frequency may be limited. If VinMAX is exceeded pulses will have to skip.
Applications requiring a high operating frequency along with a large step-down ratio require the controller to have the ability to control the smallest possible minimum on-time. For applications with a large Vin and a small Vout the minimum on-time may limit the maximum frequency.
Our new simple switcher regulators can achieve an on-time of 80ns.
The equation for the maximum switching frequency vs Vout, Vin and Ton(min) is shown.
To calculate the maximum switching frequency use:
Where VD is the diode forward drop

36. Maximum Operating Frequency vs Output Voltage
For high input voltage applications the real maximum operating frequency is determined by the minimum on-time (TON(MIN)) of the controller.
Fsw = (Vout+Vd) / (TON(MIN) x Vin)
Max operating frequency vs output voltage for the LM2557X family.
(TON(MIN) = 80ns)
Shown on this graph is a plot of max operating frequency versus output voltage for two different IC regulators with the input voltage set to 36V.
Due to the minimum on-time constraints that we discussed on the previous slide, if the input voltage is set relatively high (in this case 36V) the operating frequency may be limited, depending upon the output voltage.
Shown in blue is the maximum operating frequency versus output voltage for the LM2557X family of switching regulators. These devices are have a maximum rated operating frequency of 1MHz with a minimum on-time of 80ns.
Shown in orange is a competitor device with a maximum rated operating frequency of 2.8MHz, yet this device has a minimum on-time of 150ns. If the input voltage is set to the maximum of 36V and the output voltage is set to 3.3V this device can only operate to 700KHz, far less than the claim of 2.8MHz.
Max operating frequency vs output voltage for a “2.8MHz” device.
(TON(MIN) = 150ns)

37. Minimum Input Voltage vs Operating Frequency
A forced off-time of 500ns is implemented each cycle, to allow time for the sample & hold of the diode current. The maximum duty cycle is therefore limited to; 1 – (500ns x Fsw). For high frequency applications the minimum input voltage may be limited. If Vin is less than VinMIN the output voltage will droop.
On the past two slides we looked at how the operating frequency may be limited due to minimum duty cycle, caused by the minimum on-time.
At the other extreme, if the controller’s maximum duty cycle is limited to anything less than 100%, then the maximum operating frequency may be limited and the minimum input voltage may be limited.
For the emulated current mode control concept there is a forced off-time each cycle of 500ns. This forced off-time is necessary to allow time for the sample & hold of the diode current. This forced off-time creates a maximum duty cycle limit of 1 – (500ns x Fsw). Ideally for a buck regulator the output will remain in regulation even when the input voltage is reduced to almost equal the output voltage. The maximum duty cycle limit requires the input voltage be higher than the output voltage. The minimum input voltage predicted in the equation is lowest input voltage while the output voltage can remain in regulation.
To calculate the minimum input voltage use:
Where VD is the diode forward drop

38. Slope Compensation Background: Current mode controlled
power converters operating at duty
cycles >50% are prone to sub-harmonic
oscillation. Disturbances in peak rising
current ( I) increase at the end of the cycle.
Solution: A 25uA offset in the RAMP current source provides additional slope for the emulation ramp.
Current mode controlled power converters operating at duty cycles >50% are prone to sub-harmonic oscillation. Disturbances in peak rising current ( I) increase at the end of the cycle causing alternating large and small duty cycles.
Fortunately, the solution to the sub-harmonic issue is easy to solve. The most common solution is to add additional fixed slope to the current sense ramp. Usually the fixed slope ramp is derived from the oscillator. For the ECM control method a 25uA offset in the RAMP current source provides additional fixed slope for the emulation ramp.

39. Emulated Current Mode Advantages / Disadvantages
Reliably achieves small on-times necessary for large step-down applications.
All of the intrinsic advantages of current mode control are retained without the noise susceptibility problems often encountered from; diode reverse recovery current, ringing on the switch node and current measurement propagation delays.
During short circuit overload conditions there is no chance of a current run-away condition since the inductor current is sampled BEFORE the buck switch is turned on. If the inductor current is excessive, cycles will be skipped until the current decays below the over-current threshold.
DISADVANTAGES
In summary the emulated current mode offers all of the advantages of conventional current mode with the following advantages and disadvantages:
The maximum duty cycle is limited to less than 100% since off-time is required for the sample and hold measurement of the diode current.
If the inductor saturates, it will not be detected.

40. Constant Frequency, COT Switching Regulator
Hysteretic control is the simplest architecture available for a switcher. The modulator is simply a comparator with input hysteresis that compares the feedback voltage to a reference voltage. When the feedback voltage exceeds the reference hysteresis voltage, the comparator output goes low, turning off the switch. The switch will remain off until the feedback voltage falls below the reference hysteresis voltage, at which point, the comparator output goes high, turning on the switch and allowing the feedback voltage to rise again.
This simple topology provides several benefits. It is extremely fast at reacting to load and line transients. It has a very wide bandwidth control loop that doesn’t use an error amplifier, and doesn’t require frequency compensation. Thus, total component count is reduced, and output capacitance can be reduced.
Unlike a PWM regulator, switching frequency isn’t set by an oscillator, but is dependant on several variables.
Nearly constant operating frequency plus all of the benefits of the conventional
Constant On Time regulator.

41. Constant Frequency COT Regulator Waveforms (CCM)
Buck switch ON time:
tON = K / Vin
I RIPPLE
Buck switch turns on at the VFB threshold
Hysteretic control is also known as ripple regulation, because it is the output ripple which controls the switching. The wave forms for a hysteretic buck regulator are shown above. The inductor ripple current generates an AC voltage across the output capacitor’s ESR and ESL. This results in a triangle-shaped waveform at Vout. The output switch alternates on and off as the output waveform ramps beyond the upper and lower thresholds set by VHYS at the feedback node. Because of propagation delay, the peak to peak amplitude of the output ripple will extend slightly beyond these thresholds as shown above. Note that low ESL output capacitors must be used to keep the ripple step (seen in the Vout waveform) small and within the hysteretic window.
The equation above shows how switching frequency can be set using the external components. The output switch on time and off time (and therefore the frequency) are functions of the input and output voltage, the inductor, ESR and ESL of the output cap, the comparator’s hysteresis, the feedback ratio, and the propagation delay (td) in the modulator and output stages. When designing a regulator, we can assume that VOUT, VHYS, the resistor feedback ratio, and td are constants. As a result, we select L and ESR for a desired frequency. However, frequency will vary with input voltage, so a range of operating frequencies should be selected, given a specified range of VIN.
Stable regulation is easy to achieve by making careful selections of the inductor and output capacitor ESR. In most cases, the output capacitor’s ESR will dominate in determining both frequency and output ripple. Therefore, it is recommended that a low ESR ceramic output capacitor be used in series with a resistor to provide a stable ESR.
Output ripple can be determined by the following equation: Vrip=(Vin-Vout)*ton*ESR/L Where ton=duty cycle/frequency
V RIPPLE
Freq * tON = Vout / Vin
but tON = K / Vin
Freq * K / Vin = Vout / Vin
Freq = Vout / K = constant for given Vout

42. Synchronous Buck converter is reviewed
Summary
Synchronous Buck converter is reviewed
All critical Component and their selection criterias are highlighted.
Small-signal model of converter is developed
Various control architectures are reviewed for high-step down voltage ratios.

44. Backup

46. LM5010A High Voltage Step Down Switching Regulators
Features
Delivers 1A Continuous to Load
Operates from 6V to 75V Input Supply
Constant On-Time Control
No Control Loop Compensation
Nearly Constant Switching Frequency
Adjustable Output Voltage (2.5V – 65V)
Adjustable Soft-start
Precision 2.5V Feedback Reference
Low Bias Current (350uA, typ.)
Adjustable Valley Current Limit
Thermal Shutdown
125C Max. Junction Temperature
Package
TSSOP – 14EP (4mm x 5mm)
LLP (4mm x 4mm)

47. Operating Frequency vs Input Voltage (CCM)
Hysteretic control is also known as ripple regulation, because it is the output ripple which controls the switching. The wave forms for a hysteretic buck regulator are shown above. The inductor ripple current generates an AC voltage across the output capacitor’s ESR and ESL. This results in a triangle-shaped waveform at Vout. The output switch alternates on and off as the output waveform ramps beyond the upper and lower thresholds set by VHYS at the feedback node. Because of propagation delay, the peak to peak amplitude of the output ripple will extend slightly beyond these thresholds as shown above. Note that low ESL output capacitors must be used to keep the ripple step (seen in the Vout waveform) small and within the hysteretic window.
The equation above shows how switching frequency can be set using the external components. The output switch on time and off time (and therefore the frequency) are functions of the input and output voltage, the inductor, ESR and ESL of the output cap, the comparator’s hysteresis, the feedback ratio, and the propagation delay (td) in the modulator and output stages. When designing a regulator, we can assume that VOUT, VHYS, the resistor feedback ratio, and td are constants. As a result, we select L and ESR for a desired frequency. However, frequency will vary with input voltage, so a range of operating frequencies should be selected, given a specified range of VIN.
Stable regulation is easy to achieve by making careful selections of the inductor and output capacitor ESR. In most cases, the output capacitor’s ESR will dominate in determining both frequency and output ripple. Therefore, it is recommended that a low ESR ceramic output capacitor be used in series with a resistor to provide a stable ESR.
Output ripple can be determined by the following equation: Vrip=(Vin-Vout)*ton*ESR/L Where ton=duty cycle/frequency