1. 1 The Design of a Relay Computer Harry Porter, Ph.D. Portland State University April 24, 2006

2. 2

3. 3 +V

4. 4 Double Throw Relay

5. 5 +V Double Throw Relay

6. 6 Four Pole, Double Throw Relay

7. 7 +V Four Pole, Double Throw Relay

8. 8

9. 9 Schematic Diagrams

10. 10 Schematic Diagrams Assume other terminal is connected to ground

11. 11 Schematic Diagrams Assume other terminal is connected to ground +V

12. 12 The “NOT” Circuit inout in out 0 1 1 0 in out +V

13. 13 The “NOT” Circuit inout in out +V in out 0 1 1 0 0 1 Convention: “1” = +12V “0” = not connected

14. 14 The “NOT” Circuit inout in out +V in out 0 1 1 0 1 0 Convention: “1” = +12V “0” = not connected

15. 15 c The “OR” Circuit b b or c +V b c OUT 0 0 0 0 1 1 1 0 1 1 1 1 b c b or c

16. 16 An Optimization? c b b or c b c

17. 17 c An Optimization? b b or c b c c or d d d

18. 18 c An Optimization? b b or c b c c or d d d Whoops!

19. 19 c An Optimization? b b or c b c c or d d d Whoops!

20. 20 An Optimization? b or c c b +V d c or d b b or c c c or d d

21. 21 1-Bit Logic Circuit b c NOT b c NOT AND OR XOR 0 0 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 AND OR XOR

22. 22 1-Bit Logic Circuit b V NOT AND OR XOR c b c NOT AND OR XOR 0 0 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0

23. 23 1-Bit Logic Circuit b V c NOT AND OR XOR b c NOT AND OR XOR 0 0 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0

24. 24 1-Bit Logic Circuit b V c NOT AND OR XOR b c NOT AND OR XOR 0 0 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0

25. 25 1-Bit Logic Circuit b V c NOT AND OR XOR b c NOT AND OR XOR 0 0 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0

26. 26 1-Bit Logic Circuit b V c NOT AND OR XOR b c NOT AND OR XOR 0 0 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0

27. 27 1-Bit Logic Circuit b V c NOT AND OR XOR b c NOT AND OR XOR 0 0 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0

28. 28 1-Bit Logic Circuit b V c NOT AND OR XOR b c NOT AND OR XOR 0 0 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0

29. 29 AND 7 OR 7 Eight 1-bit circuits can be combined to build an... 8-Bit Logic Circuit Logic Circuit NOT 7 B7B7 C7C7 XOR 7 AND 1 OR 1 Logic Circuit NOT 1 B1B1 C1C1 XOR 1 AND 0 OR 0 Logic Circuit NOT 0 B0B0 C0C0 XOR 0

30. 30 The “Full Adder” Circuit Carry in Carry out Full Adder Sum BC Cy in B C Cy out Sum 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1

31. 31 Carry in Carry out Full Adder Sum BC 8 full-adders can be combined to build an... 8-Bit Adder

32. 32 8 full-adders can be combined to build an... 8-Bit Adder Carry Full Adder Full Adder B0B0 C0C0 Sum 0 Sum 1 B1B1 C1C1 Full Adder Sum 7 B7B7 C7C7 0 Carry

33. 33 8 full-adders can be combined to build an... 8-Bit Adder Carry Full Adder Full Adder B0B0 C0C0 Sum 0 Sum 1 B1B1 C1C1 Carry Full Adder Sum 7 B7B7 C7C7 + B 8 8 8 C Sum Carry 0

34. 34 The Zero-Detect Circuit Result Bus Zero V+

35. 35 The Zero-Detect Circuit Result Bus Zero V+ Sign

36. 36 Enable Circuit Enable

37. 37 Enable Circuit Enable Bus

38. 38 Enable Circuit x7x7 x6x6 x5x5 x4x4 x3x3 x2x2 x1x1 x0x0 Result Bus B XOR C Enable

39. 39 Enable Shift Left Circular (SHL) b7b7 b6b6 b5b5 b4b4 b3b3 b2b2 b1b1 b0b0 Result Bus B

40. 40 3-to-8 Decoder f 0 f 1 f 2 OUTPUT 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1

41. 41 3-to-8 Decoder f1f1 V f0f0 f2f2 f 0 f 1 f 2 OUTPUT 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1

42. 42 3-to-8 Decoder f1f1 V f0f0 f2f2 INC AND OR XOR NOT SHL ADD f 0 f 1 f 2 OUTPUT 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1 11:59

43. 43 Carry Sign Arithmetic Logic Unit (ALU) B 8 8 8 C Data Bus 3 Zero 8-bit Logic 8-bit Adder EnableEn AND OR XOR NOT SHL INC ADD Function 3-to-8 Decoder Zero-Detect

44. 44 Carry Sign An 8-Bit ALU ALU B 8 8 8 C Result Function Code 000 add 001 inc 010 and 011 or 100 xor 101 not 110 shl 111 3 Zero

45. 45 Register Storage +V A

46. 46 Register Storage +V A7A7 A0A0 A6A6

47. 47 Register Storage +V Bus Enable A7A7 A0A0 A6A6 Select

48. 48 Register Storage A7A7 Select Load A0A0 Enable A6A6 Bus

49. 49 Register Storage A7A7 Select Load A0A0 Enable A6A6 Bus

50. 50 8-Bit “Data” Bus Load Select “X” Register 8-Bit Registers

51. 51 8-Bit “Data” Bus Load Select Load Select “X” Register “Y” Register 8-Bit Registers

52. 52 16-Bit “Address” Bus 8-Bit “Data” Bus “X” Register “Y” Register Load Select Load Select Load Select

53. 53 System Architecture M1M1 M2M2 X Y 8-bit Data Bus A B C D

54. 54 System Architecture M1M1 M2M2 X Y 8-bit ALU 8-bit Data Bus ZCyS A B C D

55. 55 System Architecture A B C D M1M1 M2M2 M X Y XY 8-bit ALU 8-bit Data Bus ZCyS 16-bit Address Bus

56. 56 System Architecture A B C D M1M1 M2M2 M X Y XY 8-bit ALU 8-bit Data Bus ZCyS Inst PC 16-bit Address Bus

57. 57 System Architecture M1M1 M2M2 M X Y XY 8-bit ALU 8-bit Data Bus ZCyS Inst PC Memory Addr Data A B C D 16-bit Address Bus

58. 58 System Architecture M1M1 M2M2 M X Y XY 8-bit ALU 8-bit Data Bus ZCyS Inst PC Memory Addr Data 16-bit Increment Inc A B C D 16-bit Address Bus

59. 59 16-bit Increment Inst M1M1 M2M2 M X Y XY J1J1 J2J2 J PC Inc 8-bit ALU Memory Addr Data ZCyS System Architecture 8-bit Data Bus A B C D 16-bit Address Bus

60. 60 32K Byte Static RAM Chip LEDs 8 FET Power Transistors (to drive relays during a memory-read operation)

61. 61 16-bit Increment Inst M1M1 M2M2 M X Y XY J1J1 J2J2 J PC Inc 8-bit ALU Memory Addr Data ZCyS 8-bit Data Bus A B C D 16-bit Address Bus Example: The ALU Instruction

62. 62 16-bit Increment Inst M1M1 M2M2 M X Y XY J1J1 J2J2 J PC Inc 8-bit ALU Memory Addr Data ZCyS 8-bit Data Bus A B C D Step 1: Fetch Instruction 16-bit Address Bus

63. 63 16-bit Increment Inst M1M1 M2M2 M X Y XY J1J1 J2J2 J PC Inc 8-bit ALU Memory Addr Data ZCyS 8-bit Data Bus A B C D Step 1: Fetch Instruction SELECT 16-bit Address Bus

64. 64 16-bit Increment Inst M1M1 M2M2 M X Y XY J1J1 J2J2 J PC Inc 8-bit ALU Memory Addr Data ZCyS 8-bit Data Bus A B C D Step 1: Fetch Instruction SELECT 16-bit Address Bus

65. 65 16-bit Increment Inst M1M1 M2M2 M X Y XY J1J1 J2J2 J Inc 8-bit ALU Memory Addr Data ZCyS 8-bit Data Bus A B C D Step 1: Fetch Instruction MEM-READ PC SELECT 16-bit Address Bus

66. 66 16-bit Increment Inst M1M1 M2M2 M X Y XY J1J1 J2J2 J Inc 8-bit ALU Memory Addr Data ZCyS 8-bit Data Bus A B C D Step 1: Fetch Instruction MEM-READ PC SELECT 16-bit Address Bus

67. 67 16-bit Increment Inst M1M1 M2M2 M X Y XY J1J1 J2J2 J Inc 8-bit ALU Memory Addr Data ZCyS 8-bit Data Bus A B C D Step 1: Fetch Instruction MEM-READ PC SELECT LOAD 16-bit Address Bus

68. 68 16-bit Increment Inst M1M1 M2M2 M X Y XY J1J1 J2J2 J PC Inc 8-bit ALU Memory Addr Data ZCyS Step 1: Fetch Instruction 8-bit Data Bus A B C D MEM-READ SELECT LOAD 16-bit Address Bus

69. 69 16-bit Increment Inst M1M1 M2M2 M X Y XY J1J1 J2J2 J PC Inc 8-bit ALU Memory Addr Data ZCyS 8-bit Data Bus A B C D Step 2: Increment PC 16-bit Address Bus

70. 70 16-bit Increment Inst M1M1 M2M2 M X Y XY J1J1 J2J2 J PC Inc 8-bit ALU Memory Addr Data ZCyS 8-bit Data Bus A B C D Step 2: Increment PC SELECT 16-bit Address Bus

71. 71 16-bit Increment Inst M1M1 M2M2 M X Y XY J1J1 J2J2 J PC Inc 8-bit ALU Memory Addr Data ZCyS 8-bit Data Bus A B C D Step 2: Increment PC SELECT 16-bit Address Bus

72. 72 16-bit Increment Inst M1M1 M2M2 M X Y XY J1J1 J2J2 J PC Inc 8-bit ALU Memory Addr Data ZCyS 8-bit Data Bus A B C D Step 2: Increment PC SELECT LOAD 16-bit Address Bus

73. 73 Inst M1M1 M2M2 M X Y XY J1J1 J2J2 J PC Inc 8-bit ALU Memory Addr Data ZCyS 8-bit Data Bus A B C D Step 2: Increment PC SELECT LOAD 16-bit Increment 16-bit Address Bus

74. 74 16-bit Increment Inst M1M1 M2M2 M X Y XY J1J1 J2J2 J PC Inc 8-bit ALU Memory Addr Data ZCyS 8-bit Data Bus A B C D Step 3: Update PC 16-bit Address Bus

75. 75 16-bit Increment Inst M1M1 M2M2 M X Y XY J1J1 J2J2 J PC Inc 8-bit ALU Memory Addr Data ZCyS 8-bit Data Bus A B C D SELECT Step 3: Update PC 16-bit Address Bus

76. 76 16-bit Increment Inst M1M1 M2M2 M X Y XY J1J1 J2J2 J PC Inc 8-bit ALU Memory Addr Data ZCyS 8-bit Data Bus A B C D SELECT Step 3: Update PC 16-bit Address Bus

77. 77 16-bit Increment Inst M1M1 M2M2 M X Y XY J1J1 J2J2 J PC Inc 8-bit ALU Memory Addr Data ZCyS 8-bit Data Bus A B C D LOAD SELECT Step 3: Update PC 16-bit Address Bus

78. 78 16-bit Increment Inst M1M1 M2M2 M X Y XY J1J1 J2J2 J PC Inc 8-bit ALU Memory Addr Data ZCyS 8-bit Data Bus A B C D LOAD SELECT Step 3: Update PC 16-bit Address Bus

79. 79 16-bit Increment Inst M1M1 M2M2 M X Y XY J1J1 J2J2 J PC Inc Memory Addr Data ZCyS 8-bit Data Bus A D Step 4: Execute Instruction B C 8-bit ALU 16-bit Address Bus

80. 80 16-bit Increment Inst M1M1 M2M2 M X Y XY J1J1 J2J2 J PC Inc Memory Addr Data ZCyS 8-bit Data Bus A D Step 4: Execute Instruction FUNCTION B C 8-bit ALU 16-bit Address Bus

81. 81 16-bit Increment Inst M1M1 M2M2 M X Y XY J1J1 J2J2 J PC Inc Memory Addr Data ZCyS 8-bit Data Bus A D Step 4: Execute Instruction FUNCTION B C 8-bit ALU 16-bit Address Bus

82. 82 16-bit Increment Inst M1M1 M2M2 M X Y XY J1J1 J2J2 J PC Inc Memory Addr Data ZCyS 8-bit Data Bus A D Step 4: Execute Instruction FUNCTION B C 8-bit ALU 16-bit Address Bus

83. 83 16-bit Increment Inst M1M1 M2M2 M X Y XY J1J1 J2J2 J PC Inc Memory Addr Data ZCyS 8-bit Data Bus A D Step 4: Execute Instruction FUNCTION LOAD B C 8-bit ALU 16-bit Address Bus

84. 84 16-bit Increment Inst M1M1 M2M2 M X Y XY J1J1 J2J2 J PC Inc Memory Addr Data ZCyS 8-bit Data Bus A D Step 4: Execute Instruction FUNCTION LOAD B C 8-bit ALU 16-bit Address Bus 11:59

85. 85 Clock Switch +V Output +V

86. 86 Clock Switch +V Output +V Charging

87. 87 Clock Switch +V Output +V Discharging

88. 88 Clock Switch +V Output +V

89. 89 +V Clock +V A BCD

90. 90 +V Clock Charging +V On Discharging A BCD

91. 91 +V Clock Charging +V On Discharging On A BCD

92. 92 +V Clock Charging +V On Discharging On A BCD

93. 93 +V Clock Charging +V On Discharging On A BCD

94. 94 +V Clock Charging +V On Discharging On A BCD

95. 95 Clock Timing Diagram A B C D

96. 96 Clock Timing Diagram A B C D Clock

97. 97 Clock Timing Diagram A B C D Clock Clock = (A and B) or (C and D)

98. 98 Finite State Machine 12345678 clock

99. 99 t7t7 t5t5 t4t4 t3t3 t2t2 t1t1 Finite State Machine 12345678 t6t6 t8t8 Outputs clock

100. 100 t7t7 t5t5 t4t4 t3t3 t2t2 t1t1 Finite State Machine 12345678 t6t6 t8t8 Outputs clock

101. 101 t7t7 t5t5 t4t4 t3t3 t2t2 t1t1 Finite State Machine 12345678 t6t6 t8t8 Outputs clock

102. 102 t7t7 t5t5 t4t4 t3t3 t2t2 t1t1 Finite State Machine 12345678 t6t6 t8t8 Outputs clock

103. 103 t7t7 t5t5 t4t4 t3t3 t2t2 t1t1 Finite State Machine 12345678 t6t6 t8t8 Outputs clock

104. 104 t7t7 t5t5 t4t4 t3t3 t2t2 t1t1 Finite State Machine 12345678 t6t6 t8t8 Outputs clock

105. 105 t7t7 t5t5 t4t4 t3t3 t2t2 t1t1 Finite State Machine 12345678 t6t6 t8t8 Outputs clock

106. 106 t7t7 t5t5 t4t4 t3t3 t2t2 t1t1 Finite State Machine 12345678 t6t6 t8t8 Outputs clock

107. 107 t7t7 t5t5 t4t4 t3t3 t2t2 t1t1 Finite State Machine 12345678 t6t6 t8t8 Outputs clock

108. 108 t7t7 t5t5 t4t4 t3t3 t2t2 t1t1 Finite State Machine 12345678 t6t6 t8t8 Outputs clock

109. 109 Output from FSA 2345678123456781231 t1t1 t2t2 t3t3 t4t4 t5t5 t6t6 t7t7 t8t8

110. 110 Instruction Timing - ALU Instruction Select PC Memory Read Load Instr Load Inc Select Inc Load PC ALU Function Load A Load Cond.Code Reg. 2345678123456781231

111. 111 Instruction Timing - ALU Instruction Select PC Memory Read Load Instr Load Inc Select Inc Load PC ALU Function Load Cond.Code Reg. 2345678123456781231 Fetch Load A

112. 112 Instruction Timing - ALU Instruction Select PC Memory Read Load Instr Load Inc Select Inc Load PC ALU Function Load Cond.Code Reg. 2345678123456781231 Increment Load A

113. 113 Instruction Timing - ALU Instruction Select PC Memory Read Load Instr Load Inc Select Inc Load PC ALU Function Load Cond.Code Reg. 2345678123456781231 Load A Execute

114. 114 Instruction Decoding Instruction RegisterFinite State Machine Control Signals (Load, Select, Mem-Read, etc.) 123456 765432 10

115. 115 Instruction Decoding Instruction RegisterFinite State Machine Control Signals (Load, Select, Mem-Read, etc.) Combinational Logic 123456 765432 10

116. 116 12345678910 Instruction Timing - 16-bit Move Select PC Memory Read Load Instr Load Inc Select Inc Load PC Select Source-Register 234567811 Load Dest-Register (Same as before)

117. 117 Finite State Machine 1234567 911131516 17181920212223 101214 24 8

118. 118 Finite State Machine 1234567 911131516 17181920212223 101214 24 8

119. 119 Instruction Decoding and Control Clock Instruction Register Finite State Machine Control Lines Instruction Decoding Data Bus

120. 120 The Instruction Set (1) 0 0 d d d s s s1 0 0 0 r f f f0 1 r d d d d d1 0 1 1 0 0 0 0 Move ALU Load Immediate 16-bit Increment ddd = destination register sss = source register (A, B, C, D, M 1,M 2,X or Y) r = destination register (A or D) fff = function code (add, inc, and, or, xor, not, shl) r = destination register (A or B) ddddd = value (-16..15) XY  XY + 1

121. 121 The Instruction Set (2) 1 0 0 1 0 0 r r1 0 0 1 1 0 r r1 1 0 0 0 0 0 01 0 1 0 1 1 1 0 Load Store Load 16-bit Immediate Halt rr = destination register (A, B, C, D) reg  [M] rr = source register (A, B, C, D) [M]  reg Load the immediate value into M (i.e., M 1 and M 2 ) v v v v

122. 122 The Instruction Set (3) 1 1 1 0 0 1 1 01 0 1 0 d s s 01 0 1 0 Goto Call 16-Bit Move Return / Branch Indirect a a a a Branch to the given address 1 1 1 0 0 1 1 1a a a a Branch to the given address Save return location in XY register PC  XY d = destination register (PC or XY) ss = source register (M, XY or J)

123. 123 The Instruction Set (4) 1 1 1 1 0 0 0 0 Branch If Negative Branch If Carry Branch If Zero Branch If Not Zero a a a a Branch to the given address if S = 1 1 1 1 0 1 0 0 0a a a a Branch to the given address if Cy = 1 Branch to the given address if Z = 1 Branch to the given address if Z = 0 1 1 1 0 0 1 0 0a a a a 1 1 1 0 0 0 1 0a a a a

124. 124 An Example Program address instr assembly comment 0000 0000 0011 1001 Y=B Y  B 0000 0001 0011 0110 X=0 X  0 0000 0010 1000 0101 A=¬B If sign(Y)==1 0000 0011 1111 0000 BNEG Else. 0000 0100 0000 0000.. 0000 0101 0000 0111.. 0000 0110 0011 0010 X=C X  C Else:. 0000 0111 0101 1001 A=-7 D  -7 0000 1000 0001 1000 D=A. Loop: Loop: 0000 1001 0000 1110 B=X Shift X left (circular) 0000 1010 1000 0110 A=B<<1. 0000 1011 0011 0000 X=A. 0000 1100 0000 1111 B=Y Shift Y left (circular) 0000 1101 1000 0110 A=B<<1. 0000 1110 0011 1000 Y=A. 0000 1111 0000 1111 B=Y If sign(Y)==1 0001 0000 1000 0101 A=¬B. 0001 0001 1111 0000 BNEG Else2. 0001 0010 0000 0000.. 0001 0011 0001 0111.. 0001 0100 0000 1110 B=X X  X + C 0001 0101 1000 0000 A=B+C. 0001 0110 0011 0000 X=A. Else2:. 0001 0111 0000 1011 B=D D  D + 1 0001 1000 1000 1001 D=B+1. 0001 1001 1110 0010 BNZ Loop If D != 0 goto Loop 0001 1010 0000 0000.. 0001 1011 0000 1001.. 0001 1100 1010 1110 HALT HALT