1. Submicron Verification Challenges Uri Gruenbaum

2. Presentation Flow Chart Intro @speed Problems Case study Intro

3. Presentation Progress Intro @speed Problems Case study

4. Intro What’s going on? IC features continue to shrink. IC features continue to shrink. Fabrication processes under 130 nm Fabrication processes under 130 nm Different size generate different faults. Different size generate different faults. The faults Distribution is different The faults Distribution is different Good old Stuck-at pattern isn't Good enough. Good old Stuck-at pattern isn't Good enough. Intro @Speed Competition Case study

5. Intro In 180 nm we had: SSSStack at pattern SSSStandard memory BIST (Built in self test) IIIIddq You combine all of them and you get a coverage of ~100% Intro @speed problems Case study

6. Intro In 130 nm and less we have: HHHHigher frequencies. DDDDifferent physical properties. MMMMuch more timing defects Intro @speed problems Case study

7. Intro Intro @speed problems Did you know?  Research from LSI Logic and Intel shows that the population of timing defects for nanometer designs is ~2% Case study

8. Intro Intro @speed problems Example: 111130 nm fabrication process YYYYield average of 70% SSSStatic fault testing coverage of 100% 2222% left unchecked… 55550% of them on average are ok WWWWe will have a defect rate of 0.7% DDDDPM of 7000 Unacceptable Case study

9. Presentation Progress Intro @speed Problems Case study

10. @speed @speed Background BBBBeen available for many years AAAA timing defect test pattern UUUUsed so far to test very high speed devices & very accurate goals Intro @speed problems Case study

11. @speed-before scan @speed-before scan Intro @speed Competition Our Solution What next? clock

12. @speed- scan insertion @speed- scan insertion Intro @speed Competition Our Solution What next? clock SE SI SO

13. @speed-shift phase @speed-shift phase Intro @speed problems clock SE = 1 SI SO clock SI 110 110101 Case study

14. @speed-shift phase @speed-shift phase Intro @speed problems 011 clock SE = 1 SI SO clock SI 110 Case study

15. @speed-capture @speed-capture Intro @speed problems 011 clock SE = 0 SI SO clock SI 110 ABC ABC Case study

16. @speed-capture @speed-capture Intro @speed problems BCA clock SE = 0 SI SO clock SI 110 ABC Case study

17. @speed-shift phase @speed-shift phase Intro @speed Problems BCA clock SE = 1 SI SO clock SI 1100 0AB C Case study

18. @speed Vs Stuck at @speed Vs Stuck at Intro @speed problems Case study

19. @speed-Accurate clocks @speed-Accurate clocks Intro @speed problems Case study  There can be variations between the testers clock and the PLL clocking

20. @speed - solution @speed - solution One solution is having the ATPG (automatic test pattern generation) to decide which clock is necessary One solution is having the ATPG (automatic test pattern generation) to decide which clock is necessary Intro @speed problems Case study

21. Presentation Progress Intro Market Problems Case study

22. Problems Test patterns for transition faults are not as efficient as for stuck at faults Test patterns for transition faults are not as efficient as for stuck at faults Transition faults test = 5 times in size as a static fault test Transition faults test = 5 times in size as a static fault test When combined,expensive tester reloads is performed When combined,expensive tester reloads is performed Intro Market Problems Case study

23. Problems An interesting fact: Intro Market Problems Case study  Transition test pattern detect a significant percentage of stack at faults Starting to get the picture?

24. Problems If you need to add TFP reduce the number of SAP. If you need to add TFP reduce the number of SAP. Do it by creating the TAP first and the SAP next. Do it by creating the TAP first and the SAP next. Intro Market Problems Case study

25. Presentation Progress The Need @speed Problems Case study

26. The goal: Getting the best possible test coverage without doing expensive tester memory reloads. The Need Market problems Case study

27. Characteristic of test design: The Need Market problems Case study

28. For the design, the test requirements are : The Need Market problems Case study  Tester can hold up to 10,000 test patterns  The highest priority is to get max coverage for SAF  The test coverage for the TF must be as high as possible as long as it still fits the memory.

29. Case study Result: The Need Market problems Case study

30.  Truncating the TDF results in a significant lost in transition coverage  TDF coverage 85.14% 63.93%  Clearly not ideal The Need Market problems Case study

31. How can we improve it? The Need Market problems Case study  Recognize that for each TDF its equivalent SAF is also detected  remove the least effective patterns

32. Case study Result: The Need Market problems Case study

33. The Need Market problems Case study