1. Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 11 1 ELEC 5270/6270 Fall 2007 Low-Power Design of Electronic Circuits Adiabatic Logic Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Fall07/course.html

2. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 112 Examples of Power Saving and Energy Recovery Power saving by power transmission at high voltage: Power saving by power transmission at high voltage: 1000W transmitted at 100V, current I = 10A 1000W transmitted at 100V, current I = 10A If resistance of transmission circuit is 1Ω, then power loss = I 2 R = 100W If resistance of transmission circuit is 1Ω, then power loss = I 2 R = 100W Transmit at 1000V, current I = 1A, transmission loss = 1W Transmit at 1000V, current I = 1A, transmission loss = 1W Energy recovery from automobile brakes: Energy recovery from automobile brakes: Normal brake converts mechanical energy into heat Normal brake converts mechanical energy into heat Instead, the energy can be stored in a flywheel, or Instead, the energy can be stored in a flywheel, or Converted to electricity to charge a battery Converted to electricity to charge a battery

3. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 113 Reexamine CMOS Gate i = Ve –t/RpC /R p i 2 R p V V 2 / R p C Time, t Power Most energy dissipated here VI = V 2 e –2t/RpC / R p 0 Energy dissipation = Area / 2 = C V 2 / 2 v(t) V 3R p C

4. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 114 Charging with Constant Current i = K i 2 R p V(t) C Power 0 v(t) = Kt/C Time (T) to charge capacitor to voltage V v(T) = V = KT/C, or T = CV/K Current, i = K = CV/T Output voltage, v(t) 0 V Time, t t=CV/K Kt/C Power = i 2 R p = C 2 V 2 R p /T 2 Energy dissipation = Power × T = (R p C/T) CV 2 C 2 V 2 R p /T 2

5. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 115 Or, Charge in Steps i = Ve –t/RpC /2R p i 2 R p 0→V/2→V V 2 /4R p C Time, t Power V 2 e –2t/RpC /4R p 0 Energy = Area = CV 2 /8 v(t) V V/2 Total energy = CV 2 /8 + CV 2 /8 = CV 2 /4 3R p C6R p C

6. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 116 Energy Dissipation of a Step T E = ∫V 2 e –2t/RpC /(N 2 R p ) dt 0 = [CV 2 /(2N 2 )] (1 – e –2T/RpC ) ≈ CV 2 /(2N 2 )for large T ≥ 3R p C Voltage step = V/N

7. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 117 Charge in N Steps Supply voltage 0 → V/N → 2V/N → 3V/N →... NV/N Current, i(t) = Ve –t/RpC /NR p Power, i 2 (t)R p = V 2 e –2t/RpC /N 2 R p Energy = N CV 2 /2N 2 = CV 2 /2N→ 0 for N → ∞ Delay = N × 3R p C → ∞ for N → ∞

8. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 118 Reexamine Charging of a Capacitor V C R i(t) i(t) v(t) Charge on capacitor, q(t)=C v(t) Current, i(t)=dq(t)/dt=C dv(t)/dt t = 0

9. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 119 i(t)=C dv(t)/dt=[V – v(t)] /R dv(t)V – v(t) ───=───── dt RC dv(t) dt ∫ ─────= ∫ ──── V – v(t) RC – t ln [V – v(t)]=──+ A RC Initial condition, t = 0, v(t) = 0 → A = ln V – t v(t)=V [1 – exp(───)] RC

10. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1110 – t v(t)=V [1 – exp( ── )] RC dv(t) V – t i(t)=C ───=── exp( ── ) dt R RC

11. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1111 Total Energy Per Charging Transition from Power Supply ∞∞ V 2 – t E trans =∫ V i(t) dt=∫ ── exp( ── ) dt 00 R RC =CV 2

12. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1112 Energy Dissipated per Transition in Resistance ∞ V 2 ∞ –2t R ∫ i 2 (t) dt=R ── ∫ exp( ── ) dt 0 R 2 0 RC 1 = ─ CV 2 2

13. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1113 Energy Stored in Charged Capacitor ∞∞ – t V – t ∫ v(t) i(t) dt = ∫ V [1– exp( ── )] ─ exp( ── ) dt 00 RC R RC 1 = ─ CV 2 2

14. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1114 Slow Charging of a Capacitor V(t)V(t) C R i(t) i(t) v(t) Charge on capacitor, q(t)=C v(t) Current, i(t)=dq(t)/dt=C dv(t)/dt t = 0

15. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1115 i(t)=C dv(t)/dt=[V(t) – v(t)] /R dv(t)V(t) – v(t) ───=───── dt RC dv(t) dt ∫ ─────= ∫ ──── V(t) – v(t) RC

16. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1116 Effects of Slow Charging V(t) v(t) t Voltage across R Voltage

17. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1117 References C. L. Seitz, A. H. Frey, S. Mattisson, S. D. Rabin, D. A. Speck and J. L. A. van de Snepscheut, “Hot-Clock nMOS,” Proc. Chapel Hill Conf. VLSI, 1985, pp. 1-17. C. L. Seitz, A. H. Frey, S. Mattisson, S. D. Rabin, D. A. Speck and J. L. A. van de Snepscheut, “Hot-Clock nMOS,” Proc. Chapel Hill Conf. VLSI, 1985, pp. 1-17. W. C. Athas, L. J. Swensson, J. D. Koller, N. Tzartzanis and E. Y.-C. Chou, “Low-Power Digital Systems Based on Adiabatic-Switching Principles,” IEEE Trans. VLSI Systems, vol. 2, no. 4, pp. 398-407, Dec. 1994. W. C. Athas, L. J. Swensson, J. D. Koller, N. Tzartzanis and E. Y.-C. Chou, “Low-Power Digital Systems Based on Adiabatic-Switching Principles,” IEEE Trans. VLSI Systems, vol. 2, no. 4, pp. 398-407, Dec. 1994.

18. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1118 A Conventional Dynamic CMOS Inverter V C v(t) CK vin CK vin v(t) P E P E P E

19. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1119 Adiabatic Dynamic CMOS Inverter C v(t) CK vin A. G. Dickinson and J. S. Denker, “Adiabatic Dynamic Logic,” IEEE J. Solid-State Circuits, vol. 30, pp. 311-315, March 1995. CK vin v(t) V0V0 V-Vf 0 Vf + P E P E

20. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1120 Cascaded Adiabatic Inverters CK1CK2CK1’CK2’ vin CK1 CK2 CK1’ CK2’ precharge input evaluate hold

21. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1121 Complex ADL Gate CK B A. G. Dickinson and J. S. Denker, “Adiabatic Dynamic Logic,” IEEE J. Solid-State Circuits, vol. 30, pp. 311-315, March 1995. A C AB + C Vf < Vth

22. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1122 Quasi-Adiabatic Logic Two sets of diodes: One controls the charging path (D1) while the other (D2) controls the discharging path Two sets of diodes: One controls the charging path (D1) while the other (D2) controls the discharging path Supply lines have EVALUATE phase (  swings up) and HOLD phase (  swings up) Supply lines have EVALUATE phase (  swings up) and HOLD phase (  swings up) D1 Y. Ye and K. Roy, “QSERL: Quasi-Static Energy Recovery Logic,” IEEE J. Solid-State Circuits, vol. 36, pp. 239-248, Feb. 2001.

23. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1123 Clocks EVAL. HOLD   0 0 V DD

24. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1124 Possible Cases: The circuit output node X is LOW and the pMOS tree is turned ON: X follows  as it swings to HIGH (EVALUATE phase) The circuit node X is LOW and the nMOS tree is ON. X remains LOW and no transition occurs (HOLD phase) The circuit node X is HIGH and the pMOS tree is ON. X remains HIGH and no transition occurs (HOLD phase) The circuit node X is HIGH and the nMOS tree is ON. X follows  down to LOW. Quasi-Adiabatic Logic Design

25. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1125 A Case Study K. Parameswaran, “Low Power Design of a 32-bit Quasi-Adiabatic ARM Based Microprocessor,” Master’s Thesis, Dept. of ECE, Rutgers University, New Brunswick, NJ, 2004.

26. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1126 Quasi-Adiabatic 32-bit ARM Based Microprocessor Design Specifications Operating voltage: 2.5 V Operating voltage: 2.5 V Operating temperature: 25 o C Operating temperature: 25 o C Operating frequency: 10 MHz to 100 MHz Operating frequency: 10 MHz to 100 MHz Leakage current: 0.5 fAmps Leakage current: 0.5 fAmps Load capacitance: 6X10 -18 F (15% activity) Load capacitance: 6X10 -18 F (15% activity) Transistor Count: Transistor Count:

27. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1127 Technology Distribution Microprocessor has a mix of static CMOS and Quasi-adiabatic components Microprocessor has a mix of static CMOS and Quasi-adiabatic components ALU Adder-subtractor unit Barrel shifter unit Booth-multiplier unit Control Units ARM controller unit Bus control unit Pipeline Units ID unit IF unit WB unit MEM unit Quasi-AdiabaticStatic CMOS

28. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1128 Power Analysis DatapathComponent Power Consumption (mW) Frequency 25 MHz Power Consumption (mW) Frequency 100 MHz Quasi- adiabatic Static CMOS Power Saved Quasi- adiabatic Static CMOS Power Saved 32-bit Adder Subtracter 1.011.5544%1.291.6220% 32-bit Barrel Shifter 0.91.68146%1.3681.824% 32-bit Booth Multiplier 3.45.840%5.156.217% Power Consumption (mW) Frequency 25 MHz Quasi- adiabatic Static CMOS Power Saved 60 mW 85 mW 40%

29. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1129 Power Analysis (Cont’d.)

30. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1130 Area Analysis DatapathComponent Area (mm 2 ) Quasi- adiabatic Static CMOS Area Increase 32-bit Adder Subtracter 0.050.0366% 32-bit Barrel Shifter 0.250.11120% 32-bit Booth Multiplier 1.20.5140% Chip Area (mm 2 ) Quasi- adiabatic Static CMOS Area Increase 1.551.0144%

31. Copyright Agrawal, 2007ELEC6270 Fall 07, Lecture 1131 Summary In principle, two types of adiabatic logic designs have been proposed: In principle, two types of adiabatic logic designs have been proposed: Fully-adiabatic Fully-adiabatic Adiabatic charging Adiabatic charging Charge recovery: charge from a discharging capacitor is used to charge the capacitance from the next stage. Charge recovery: charge from a discharging capacitor is used to charge the capacitance from the next stage. W. C. Athas, L. J. Swensson, J. D. Koller, N. Tzartzanis and E. Y.-C. Chou, “Low-Power Digital Systems Based on Adiabatic-Switching Principles,” IEEE Trans. VLSI Systems, vol. 2, no. 4, pp. 398-407, Dec. 1994. W. C. Athas, L. J. Swensson, J. D. Koller, N. Tzartzanis and E. Y.-C. Chou, “Low-Power Digital Systems Based on Adiabatic-Switching Principles,” IEEE Trans. VLSI Systems, vol. 2, no. 4, pp. 398-407, Dec. 1994. Quasi-adiabatic Quasi-adiabatic Adiabatic charging and discharging Adiabatic charging and discharging Y. Ye and K. Roy, “QSERL: Quasi-Static Energy Recovery Logic,” IEEE J. Solid-State Circuits, vol. 36, pp. 239-248, Feb. 2001. Y. Ye and K. Roy, “QSERL: Quasi-Static Energy Recovery Logic,” IEEE J. Solid-State Circuits, vol. 36, pp. 239-248, Feb. 2001.