1. Computer Architecture: A Constructive Approach Instruction Representation Arvind Computer Science & Artificial Intelligence Lab. Massachusetts Institute of Technology January 13, 2012L5-1 http://csg.csail.mit.edu/SNU

2. Single-Cycle SMIPS PC Inst Memory Decode Register File Execute Data Memory +4 Datapath is shown only for convenience; it will be derived automatically from the high- level textual description January 13, 2012 L5-2http://csg.csail.mit.edu/SNU

3. immValid Decoding Instructions: extract fields needed for execution from each instruction instruction branchComp rDst rSrc1 rSrc2 imm ext aluFunc instType 31:26 5:0 31:26 20:16 15:11 25:21 20:16 15:0 25:0 Lot of pure combinational logic: will be derived automatically from the high-level description decode January 13, 2012 L5-3http://csg.csail.mit.edu/SNU

4. decode Decoding Instructions: input-output types instruction branchComp rDst rSrc1 rSrc2 imm ext aluFunc instType 31:26 5:0 31:26 20:16 15:11 25:21 20:16 15:0 25:0 Type DecBundle Instr IType Func Rindex BrType Bits#(32) Mux control logic not shown immValid : Bool January 13, 2012 L5-4http://csg.csail.mit.edu/SNU

5. Type defs typedef enum {RAlu, IALU, Ld, St, …} IType deriving(Bits, Eq); typedef enum {Eq, Neq, Le, Lt, Ge, Gt, J, JR, N} BrType deriving(Bits, Eq); typedef enum {Add, Sub, And, Or, Xor, Nor, Slt, Sltu, LShift, RShift, Sra} Func deriving(Bits, Eq); January 13, 2012 L5-5http://csg.csail.mit.edu/SNU

6. Instruction grouping Many instructions have the same implementation except for the ALU function they invoke We can group such instructions and reduce the amount of code we have to write Example: R-Type ALU, I-Type ALU, Br Type, Memory Type, … January 13, 2012 L5-6http://csg.csail.mit.edu/SNU

7. Decoding Instructions function DecodedInst decode(Bit#(32) inst, Addr pc); DecodedInst dInst = ?; let opcode = instrBits[ 31 : 26 ]; let rs = instrBits[ 25 : 21 ]; let rt = instrBits[ 20 : 16 ]; let rd = instrBits[ 15 : 11 ]; let shamt = instrBits[ 10 : 6 ]; let funct = instrBits[ 5 : 0 ]; let imm = instrBits[ 15 : 0 ]; let target = instrBits[ 25 : 0 ]; case (instType(opcode))... endcase return dInst; endfunction January 13, 2012 L5-7http://csg.csail.mit.edu/SNU

8. Decoding Instructions: R-Type ALU case (instType(opcode)) … RAlu: begin dInst.instType = Alu; dInst.aluFunc = case (funct) fcADDU: Add fcSUBU: Sub... endcase; dInst.rDst = rd; dInst.rSrc1 = rs; dInst.rSrc2 = rt; dTnst.immValid = False end January 13, 2012 L5-8http://csg.csail.mit.edu/SNU

9. Decoding Instructions: I-Type ALU case (instType(opcode)) … IAlu: begin dInst.instType = Alu; dInst.aluFunc = case (opcode) opADDUI: Add... endcase; dInst.rDst = rt; dInst.rSrc1 = rs; dInst.imm = signedIAlu(opcode) ? signExtend(imm): zeroExtend(imm); dTnst.immValid = True end January 13, 2012 L5-9http://csg.csail.mit.edu/SNU

10. Decoding Instructions: Load & Store case (instType(opcode)) LW: begin dInst.instType = Ld; dInst.aluFunc = Add; dInst.rDst = rt; dInst.rSrc1 = rs; dInst.imm = signExtned(imm); dTnst.immValid = True end SW: begin dInst.instType = St; dInst.aluFunc = Add; dInst.rDst = rt; dInst.rSrc1 = rs; dInst.imm = signExtned(imm); dTnst.immValid = True end January 13, 2012 L5-10http://csg.csail.mit.edu/SNU

11. Decoding Instructions: Jump case (instType(opcode)) … J, JAL: begin dInst.instType = opcode==J ? J : Jal; dInst.rDst = 31; dInst.imm = zeroExtend({target, 2’b00}); dTnst.immValid = True end rJump: begin dInst.instType = funct==JR ? Jr : Jalr; dInst.rDst = rd; dInst.rSrc1 = rs; end January 13, 2012 L5-11http://csg.csail.mit.edu/SNU

12. Decoding Instructions: Branch case (instType(opcode)) … Branch: begin dInst.instType = Br; dInst.branchComp = case (opcode) opBEQ: EQ opBLEZ: LE... endcase; dInst.rSrc1 = rs; dInst.rSrc2 = rt; dInst.imm = signExtend({imm, 2’b00}); dTnst.immValid = True end January 13, 2012 L5-12http://csg.csail.mit.edu/SNU

13. Decoding Not all fields of dInst are defined in each case We may decide to pass more information from decode to execute for efficiency– in that case the definition of the type of the decoded instruction has to be adjusted accordingly January 13, 2012 L5-13http://csg.csail.mit.edu/SNU

14. Single-Cycle SMIPS module mkProc(Proc); Reg#(Addr) pc <- mkRegU; RFile rf <- mkRFile; Memory mem <- mkMemory; rule fetchAndExecute; //fetch let instResp <- mem.iside(MemReq{op:Ld, addr:pc, data:?}); //decode let decInst = decode(instResp); Data rVal1 = rf.rd1(decInst.rSrc1); Data rVal2 = rf.rd2(decInst.rSrc2);  14 January 13, 2012 L5-14http://csg.csail.mit.edu/SNU

15. //execute let execInst = exec(decInst, pc, rVal1, rVal2); if(execInst.instType==Ld || execInst.instType==St) execInst.data <- mem.dside( MemReq{op:execInst.instType, addr:execInst.addr, data:execInst.data}); pc <= execInst.brTaken ? execInst.addr : pc + 4; //writeback if(execInst.instType==Alu || execInst.instType==Ld) rf.wr(execInst.rDst, execInst.data); endrule endmodule;  Single-Cycle SMIPS cont January 13, 2012 L5-15http://csg.csail.mit.edu/SNU

16. Executing Instructions  16 execute decInst addr brTaken data instType rDst ALU Branch Address pc rVal2 rVal1 Pure combinational logic either for memory reference or branch target either for rf write or St January 13, 2012 L5-16http://csg.csail.mit.edu/SNU

17. Executing Instructions function ExecInst exec(DecodedInst dInst, Addr pc, Data rVal1, Data rVal2); Data aluVal2 = (dInst.immValid)? dInst.imm : rVal2 let aluRes = alu(rVal1, aluVal2, dInst.aluFunc); let brRes = aluBr(rVal1, aluVal2, dInst.brComp); let brAddr = brAddrCal(pc, rVal1, dInst.instType, dInst.imm); return ExecInst{ instType: dInst.instType, brTaken: brRes, addr: dInst.instType==(Ld || St) ? aluRes : br.addr, data: dInst.instType==St ? rVal2 : aluRes, rDst: dInst.rDst}; endfunction  17 January 13, 2012 L5-17http://csg.csail.mit.edu/SNU

18. Branch Resolution function Address brAddrCal(Address pc, Data val, InstType iType, Data imm); let targetAddr = case (iType) J : {pc[31:26], imm[25:0]} JR : val default: pc + imm endcase; return targetAddr; endfunction  18 January 13, 2012 L5-18http://csg.csail.mit.edu/SNU

19. Single-Cycle SMIPS PC Inst Memory Decode Register File Execute Data Memory +4 The whole system was described using one rule; lots of big combinational functions performance? January 13, 2012 L5-19http://csg.csail.mit.edu/SNU

20. Next few lectures Can we build a faster machine? What if program and data resided in the same memory What if the register file did not have adequate number of ports January 13, 2012 L5-20http://csg.csail.mit.edu/SNU