1. Datapath and Control Andreas Klappenecker CPSC321 Computer Architecture

2. Administrative Issues Exam has been graded Grades need to be entered by TA Attendance in the labs Lab 3 assignment Make-up exam T 2:00pm-2:50pm

3. Goal of this lecture Revisit the single-cycle processor datapath control Why are the instructions structured in the way they are? Multi-cycle processor

4. The Single-Cycle Processor Revisited

5. Instruction Word Formats Register format Immediate format Jump format op-code rs rt rd shamt funct op-code rs rt immediate value op-code 26 bit current segment address 6 55 16 6 555 5 6 6 26

6. Hardware components

7. Datapath for MIPS instructions Seven control signals

8. Datapath Each instruction type required some hardware components Designed the datapaths for the different instruction types Merged the datapaths reuse hardware whenever possible use multiplexors to combine datapaths

9. R-Format Instructions Register format op-code rs rt rd shamt funct 6 555 5 6

10. Datapath for a load and store 1. register access 2. memory access calculation 3. read or write from memory 4. in the case of a load, write into register file

11. Datapaths for Instruction Fetch, Memory and R-type Instructions xtend ALU result Zero ALU Address RegWrite ALU operation 3 MemRead MemWrite ALUSrc MemtoReg xtend ALU result Zero ALU Address RegWrite ALU operation 3 MemRead MemWrite ALUSrc MemtoReg xtend ALU result Zero ALU Address RegWrite ALU operation 3 MemRead MemWrite ALUSrc MemtoReg Note the added multiplexor switching between register 2 and sign-extended immediate value

12. Control Selecting the operations to perform (ALU, read/write, etc.) Controlling the flow of data (multiplexor inputs) Information comes from the 32 bits of the instruction Example: add $8, $17, $18 Instruction Format: 000000 10001 10010 01000 00000100000 op rs rt rd shamt funct ALU's operation based on instruction type and function code

13. For example, what should the ALU do with this instruction? lw $1, 100($2) 35 2 1 100 op rs rt 16 bit offset Control

14. ALU Control Logic ALU cntrlFunction 000and 001or 010add 110sub 111slt Depending on instruction, the ALU has to perform one of the five operations Why is the control for sub 110 and not 011?

15. ALU Control

16. Control

17. Multi-Cycle Processor

18. Performance Improvement Fixed cycle time obviously inefficient Variable cycle time faster timing more complex Multiple Clock Cycles break up instructions into one-cycle steps balance amount of work to be done restrict each cycle to use only one major functional unit store values at end of cycle for use in later cycles

19. Reuse functional units ALU used to compute address and to increment PC Memory used for instruction and data Control signals not just determined by instruction additional complexity is introduced here Finite state machine can be used for control Multicycle Approach

20. Multicycle Datapath

21. Outlook Discuss the details of the datapath Instruction fetch/decode/execute cycle Construct the finite state machine for control More complicated processors: Use microprogramming to simplify control

22. Finite state machines: a set of states and next state function (determined by current state + input) output function (determined by current state + input) Moore machine (output based only on current state) Finite State Machines