1. ATM over SONET/SDH Fiksman Evgeny Gurovich Alexander DigLab Seminar

2. Problems to solve Each pair of multiplexors (A - A’) in the system has to be manufactured by the same supplier. Access to a single tributary circuit, demands demultiplexing the whole structure and then remultiplexing. The multiplexing structure different in some countries. There is an enormous cost benefit in removing the multiplexors entirely.

3. Synchronous Optical Network The basic structure in Sonet is a frame of 810 bytes (STS- 1). Sent every 125  sec - minimum speed 51.84 Mbps The first three columns of every row are used for administration and control of the multiplexing system.

4. Sonet Synchronous Payload Envelope SPE is pointed by H1, H2. Small differences in the clock are accommodated by H3 pointer. Multiple STS-1 frames can be byte-multiplexed together. Four STS-1 to STS-4 phase-aligned with their payloads. Four STS-1 to STS-4c.

5. Synchronous Digital Hierarchy STM-1 is STS-3c Minimum speed 155.52 Mbps Accommodates both US and the European line speeds. Faster line speeds are obtained in the same way as in Sonet - by byte interleaving of multiple STM-1 frames. Four STM-1 frames may be multiplexed to form an STM-4 or STM-4c at 622.08 Mbps.

6. Asynchronous Transfer Mode Data transferred in small packets called “cells” Information flow is along paths called “virtual channels”. ATM is designed to make hardware switching simple. At the edges of the network, user data frames are broken up into cells. The ATM cell switching network only checks cell headers for errors (HEC) and simply discards errored cells.

7. ATM over SDH physical interface Cells are transmitted row by row without regard to row or cell boundaries. There are a number of end-to-end TDM channels across the link, independent of the main channel - primary function of SOH & LOH. Three standards:  Sonet STS-3c  STM-1  Sonet “Lite” In the early specifications H4 points to the cell boundary. Now cell delineation done only by the HEC method.

8. HEC method for cell delineation HCS is a CRC-8 calculation over the first 4 octets of the ATM cell header. While searching for the cell boundary location, the cell delineation circuit is in the HUNT state. On correct HCS the cell delineation state machine locks on the particular cell boundary and enters the PRESYNC state. If no HCS errors are detected in this PRESYNC period then the SYNC state is entered.

9. Bibliography Asynchronous Transfer Mode (ATM) Technical Overview - IBM, International Technical Support Organization, SG24-4625-00. PMC - PM5346 Datasheet.