1. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 1 Chapter 10 Pentium™ Processor Fundamentals PC Architecture for Technicians: Level-1 Systems Manufacturing Training and Employee Development Copyright © 1996 Intel Corp.

2. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 2 Introduction l The knowledge acquired here about the Pentium™ processor features, architecture, signals and key bus cycles will serve a foundation for the boards based on this processor. l This overview will describe the features of the Pentium as used in a typical Single Processor PC system in Real Mode. n Multiprocessor support signals and MESI protocol signals are beyond the scope of this course. n Protected Mode Registers and related features are beyond the scope of this course.

3. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 3 l Describe the basic architecture of the Pentium processor. l Explain the use of the Pentium Registers. l Describe the various Pentium buses. l Explain the use of the Byte Enables. l Discuss Pentium address generation. l Discuss Pentium Bus Cycle Definitions. l Describe Pentium Single & Burst cycles. l Discuss Pentium Signal Descriptions. OBJECTIVES: At the end of this section, the student will be able to do the following:

4. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 4 Intel Family Comparison

5. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 5 The Intel 86 Family of Processors ProcessorsYear Internal Architecture External Bus Size TransistorsPrinciple Features 86197816 29K16-bit architecture, basic segment protection 8819798829KSame as 86, but with 8-bit processor bus. (IBM PC) 286198216 130KExpands segmentation protection, adds single- instruction task switching (used in IBM PC/AT) Intel 386 TM 198532 375K Adds paging, 32-bit extensions, on-chip address translation, and greater speed to 286 functions Intel 386 TM SX 19883216375K Same as Intel 386 processor, but with a 16-bit data bus

6. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 6 ProcessorsYear Internal Architecture External Bus Size TransistorsPrinciple Features Intel 486 TM DX 198932 1,200KAdds on-chip cache, floating- point unit, and greater speed to Intel386 TM 1991Intel486 TM SX 32 No math, Lower cost The Intel TM 86 Family of Processors Intel486 TM DX-2 199232 1.2 MegDouble internal speed Pentium TM P5 - 60,66 326419933.1 Meg Superscaler, Code & Data Cache, 64 bit data bus 6432 Pentium TM P54C 1994 3.3 Meg 3.3v, Power Mgt, Multiprocessor support 6432 Pentium TM Pro 1995CPU 5.5 Meg On Chip L1 & L2, Dynamic Execution GTL logic

7. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 7 Intel Family Comparison

8. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 8 THE iCOMP (TM) INDEX l iCOMP n (Intel COmparative Microprocessor Performance). l The iCOMP index is a simple numerical index of relative performance for making straightforward comparisons of Intel CPU power. n The base processor for the iCOMP index is the 25-MHz Intel486 TM SX processor, which has been assigned a value of 100. n The size of the disparity between any two indices provides a relative measure of how much more powerful one CPU is than any other. l It is an index that reflects the relative performance of one Intel microprocessor to another, not system performance.

9. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 9 Pentium™ Processor Architecture

10. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 10 Pentium™ Processor Architecture Divide Add 64 bit bus Interface Code Cache Prefetch Buffers Integer ALU Register Set Data Cache Branch Prediction Pipelined Floating-Point Unit Multiply U pipe V pipeline 32 bits 64 bits 256 bits

11. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 11 l The Pentium processors have a data bus of 64 bits. n This is a 32 bit CPU due to having 32 bits registers. n A standard Single Transfer Cycle can read or write up to 64 bits at a time (8 bytes) l Burst read and burst write-back cycles are supported by the Pentium processors. n Burst Mode cycles are used for Cache operations and transfer 32 bytes in 4 clocks (4 * 8 bytes = 4 * 64 bits). 3 32 bytes is the size of the Pentium Cache line. n For the Pentium, all cache operations are burst cycles. Pentium™ Processor Architecture

12. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 12 32 bits 64 bits 256 bits Separate Code and Data caches On chip 8KB code and 8KB write back data cache. Two way set associative. MESI Cache protocol Divide Add 64 bit bus Interface Prefetch Buffers Code Cache Integer ALU Register Set Data Cache Branch Prediction Pipelined Floating-Point Unit Multiply U pipeline V pipeline Pentium™ Processor Architecture

13. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 13 l Pentium processors include separate Code and Data Caches which can be enabled or disabled by software or hardware. n Each cache is 8-Kbytes in size, with a 32-byte line size and is 2-way set associative (4K/way). n The Data Cache is configurable to be write-back or write-through on a line-by-line basis and follows MESI protocol. n The Instruction Cache is an inherently write-protected cache (read-only) Pentium™ Processor Architecture

14. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 14 Divide Add 64 bit bus Interface Code Cache Prefetch Buffers Integer ALU Register Set Data Cache Branch Prediction Pipelined Floating-Point Unit Multiply U pipeline V pipeline 32 bits 64 bits 256 bits Pipeline sequence Prefetch Decode1 Decode2 Execute Write Back Branch prediction: Processor makes predictions on next instruction to be executed via the BTB. Hardwired Instructions Technical Innovations... Pentium™ Processor Architecture Superscalar Architecture more than one execution unit NOTE: The Instruction Decode Unit is in the Prefetch Buffers on this diagram.

15. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 15 l Instructions are Fetched from the code cache or from the external bus. l The decode unit Decodes the prefetched instructions so the Pentium processor can execute the instruction. n Branch prediction is implemented with 2 Prefetch Buffers and a Branch Target Buffer so the needed code is almost always prefetched before it is needed for execution. l Instructions are executed in 1 of 2 pipelines (“u” & “v” pipes) which share access to a single set of registers. n No additional instructions can begin execution until both execution units complete their operations. Pentium™ Processor Architecture

16. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 16 Pentium™ Processor Architecture l Pentium processors have two instruction pipelines. n The u-pipe can Execute all integer and floating point instructions. n The v-pipe can Execute simple integer instructions and the FXCH floating-point instructions. n Pairing instructions in these two pipes enables the Pentium to operate on 2 instructions at the same time (Superscaler execution). l The Control ROM unit has direct control over both pipelines. n The Control ROM contains microcode which controls the sequence of operations that must be performed.

17. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 17 Pentium™ Processor Registers

18. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 18 Pentium Registers 0 7152331 16-BIT32-BIT AX DX CX BX EAX EDX ECX EBX EBP ESI EDI ESP Segment Registers General Registers 168 CS SS DS ES FS GS AH DH CH BH AL DL CL BL EFLAGS EIP Status and Control 031 NOTE: All registers in REAL MODE DEFAULT to 16 bits wide.

19. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 19 Segmented Addressing Code Segment Stack Segment Data Segment Data Segment Data Segment Data Segment CS DS SS ES FS GS

20. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 20 Segmented Addressing Segment Register Offset within segment 0 15 0 Operand e.g - CS e.g - IP NOTE: We will assume, unless otherwise stated, that all examples reflect real mode.

21. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 21 Pentium Registers (EFlags) l The EFlags register is not a normal register but a collection of FLAG BITS which indicate the result of previous operations or the current state of the CPU. n A FLAG is just a flip-flop in the CPU that is SET (1) or RESET (0) [cleared] depending on the condition produced by an instruction. n Some Flags indicate the condition produced by the previous instruction. 3 e.g - Zero Flag: ZF=1 (True) if the result of the last arithmetic or logical operation was Zero. n Some Flags are used to control certain operations. 3 e.g. - IF (Interrupts Enabled); Trap Flag; Direction Flag.

22. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 22 Pentium Registers (EFlags) IDXID Flag (CPUID support) VIPXVirtual Interrupt Pending VIFXVirtual Interrupt Flag ACXAlignment Check VMXVirtual 8086 Mode RFXResume Flag NTXNested Task IOPLXI/O Privilege Level OFSOverflow Flag DFCDirection Flag IFXInterrupt Enable Flag TFXTrap Flag SFSSign Flag ZFSZero Flag AFSAuxiliary Carry Flag PFSParity Flag CFSCarry Flag S = Status Flag C = Control Flag X = System Flag Bit Positions shown as “0” or “1” are Intel reserved. 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDID IDID VIPVIP VIPVIP VIFVIF VIFVIF ACAC ACAC VMVM VMVM RFRF RFRF 0 0 NTNT NTNT IOPLIOPL IOPLIOPL IOPLIOPL IOPLIOPL OFOF OFOF DFDF DFDF IFIF IFIF TFTF TFTF SFSF SFSF ZFZF ZFZF 0 0 AFAF AFAF 0 0 PFPF PFPF 23 1 1 157 CFCF CFCF FLAGS

23. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 23 Pentium Registers Pentium Registers (Debug) B3B3 B2B2 B1B1 B0B0 BTBT BSBS BDBD GDGD DR3 - Breakpoint 3 Linear Address DR2 - Breakpoint 2 Linear Address DR1 - Breakpoint 1 Linear Address DR0 - Breakpoint 0 Linear Address LEN 3 R/W 3 LEN 2 R/W 2 R/W 1 R/W 0 LEN 1 LEN 0 GEGE LELE G3G3 L3L3 G2G2 L2L2 G1G1 L1L1 G0G0 L0L0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0 10 Reserved

24. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 24 Pentium Registers Pentium Registers (Debug) l The Debug Registers provide hardware support for setting breakpoints. l You can define up to four breakpoints using Debug Registers (DR0 - DR3). l The Debug Registers store the Linear Address. n The linear address is the address after the addition of the Segment Base & the Offset (w/o Paging). 3 This is the Physical Address in REAL MODE. l When the Pentium address matches an address in one of the Debug Registers, the Pentium issues a Debug Exception (INT 1). n This feature is used with the ITP Debug Tool.

25. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 25 Pentium™ Bus Description

26. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 26 Bus Description Pentium™ Processor 64 bit Memory D63:0 A31:3, BE7#:0# Pentium™ Processor with 64 Bit Wide Memory

27. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 27 Bus Description Byte Low Byte High Byte Low WordHigh Word Low Doubleword High Doubleword 0 7 0 15 31 0715 31 Address N Address N+1 Address N Address N Address N+1 Address N+2 Address N+3 0 15 4763 Byte Word Doubleword Address N Address N+1 Address N+2 Address N+3 Address N+4 Address N+5 Address N+6 Address N+7 Data Types Each location in memory is Byte wide Quadword “Chunk”

28. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 28 Bus Description FFFFFFF8HFFFFFFFFH 00000000H00000007H PHYSICAL MEMORY 4GB Physical Memory Space FFFFFFF8HFFFFFFFFH 00000007H00000000H BE7#BE6#BE5#BE4#BE3#BE2#BE1#BE0# 64-BIT Wide Memory Organization

29. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 29 CPU Bus Description 00000000H 00000003H I/O Space 64 KByte Not Accessible 0000FFFCH 0000FFFFH l I/O Address Space is limited to 64 Kbytes (0000H-FFFFH). l This limit is imposed by a 16 bit CPU Register. n A 16 bit register can store up to FFFFH (1111 1111 1111 1111 y). l Which CPU Register limits I/O space to 64K?

30. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 30 CPU Bus Description l Address bus: The microprocessor provides an address to the memory & I/O chips. n The number of address lines determines the amount of memory supported by the processor. n A31:A3 Address bus lines (output except for cache snooping) determines where in the 4GB memory space or 64K I/O space the processor is accessing.

31. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 31 CPU Bus Description l The Pentium address consists of two sets of signals: n Address Bus (A31:3) n Byte Enables (BE7#:0#) l Since address lines A2:0 do not exist on the Pentium, the CPU uses A31:3 to identify a group of 8 locations known as a Quadword (8 bytes -- also know as a “chunk” ). n Without A2:0, the CPU is only capable of outputting every 8th address. (e.g. 00H, 08H, 10H, 18H, 20H, 28H, etc.) 3 A2:0 could address from 000 to 111 in binary (0-7H) 3 = 011 7 = 111 2 = 010 6 = 110 1 = 001 5 = 101 0 = 000 4 = 100

32. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 32 Example Addresses Output by CPU Output on CPU Address Lines for addresses within a Quadword Addresses 00000000 - 000000F

33. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 33 Example Addresses Output by CPU Output on CPU Address Lines for addresses within a Quadword Addresses 00000010 - 000001F

34. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 34 CPU Bus Description l The Pentium uses Byte Enables to address locations within a QWORD. n BE7#:BEO# (outputs): Byte enable lines - to enable each of the 8 bytes in the 64-bit data path. n In effect a decode of the address lines A2-A0 which the Pentium does not generate. n Which lines go active depends on the address, and whether a byte, word, double word or quad word is required.

35. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 35 Relationship of Byte Enables to Locations Addressed within a QWORD

36. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 36 Pentium Processor Addressing Examples l Relationship of Addresses, Byte Enables, and locations accessed. n 1 byte @ 12301000 (BE0#) n 1 word starting at FE025606 (BE7# & BE6#) n 8 bytes starting at 80000108 (BE7# through BE0#) n 1 word starting at 0A5D0F0D (BE6# & BE5#) Addr A31:3 12301000 FE025600 80000108 0A5D0F08 Locations Addressed 12301000 FE025606, FE025607 80000108 - 8000010F 0A5D0F0D, 0A5D0F0E BE7#BE6#BE5#BE4#BE3#BE2#BE1#BE0# 11111110 00111111 00000000 10011111 7F7F 6E6E 5D5D 4C4C 3B3B 2A2A 1919 0808

37. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 37 Pentium Processor Addressing Examples l Example Assembly Language Instructions and the resultant Addresses & Byte Enables. (Assume DS=0) n MOV AL, [0100] -1 byte @ 00000100 (BE0#) n MOV BH, [0105] -1 byte @ 00000105 (BE5#) n MOV AX, [0104] - 1 word starting at 00000104 (BE4# & BE5#) n MOV EAX, [0100] -1 dword starting at 00000100 (BE0# through BE3#) BE7#BE7# BE6#BE6# BE5#BE5# BE4#BE4# BE3#BE3# BE2#BE2# BE1#BE1# BE0#BE0# 11111110 11011111 11001111 11110000 Instruction MOV AL, [0100] MOV BH, [0105] MOV AX, [0104] MOV EAX, [0100] Addr on A31:3 00000100 Locations Addressed 00000100 - 8 BIT 00000105 - 8 BIT 00000104, 00000105 - 16 BIT 00000100 TO 00000103 - 32 BITS 107 ------------------- 100

38. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 38 CPU Bus Description Data bus: The data bus provides a path for data to flow. l The data can flow to/from the microprocessor during a memory or I/O operation. n D63:DO (bi-directional): The 64-bit data path to or from the processor. The signal W/R# distinguishes direction. l Control bus: The control bus is used by the CPU to tell the memory and I/O chips what the CPU is doing. n Typical control bus signals are these: 3 ADS# (output): Signals that the processor is beginning a bus cycle: 3 BRDY# (input): This signal ends the current bus cycle and is used to extend bus cycles. (Ready Logic next page)

39. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 39 TW= Time Wait Ready Logic State Machine Example

40. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 40 CPU Bus Description l Control bus:(Cont.) n Typical control bus signals are these: (Cont.) 3 M/IO# (output): Defines if the bus cycle is a Memory access or an Input/Output Port access. 3 D/C# (output): Defines if the bus cycles is Data or Code for Memory access. 3 W/R# (output): Indicates if bus cycle is a Write or a Read operation. 3 Cache#. (output): Processor indication of internal cacheability. Cache# and Ken# are used together to determine of a read will be turned into a linefill. (Burst cycle).

41. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 41 Pentium™ Bus Cycles

42. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 42 Bus Cycles Definition driven high.

43. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 43 GENERIC DECODE LOGIC l The system board contain some logic to decode the BUS CYCLE DEFINITIONS of the CPU. l The BUS CYCLE DEFINITIONS from the CPU are VALID when ADS# is asserted (Logic 0). l The drawing shows an example of logic that could be used to decode the BUS CYCLE DEFINITIONS. l The signals generated by the GENERIC DECODE LOGIC would be used by the System Board to generate signals such as I/O chip selects and DRAM & PROM output enables.

44. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 44 GENERIC DECODE LOGIC e.g. I/O WR @ Addr 43H 43H = 0100 0011y M/IO#

45. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 45 GENERIC DECODE LOGIC e.g. I/O WR @ Addr 43H 43H = 0100 0011y (0 0 0) (0 0 1) ( 0 1 0) (0 1 1) (1 0 0) (1 0 1) (1 1 0) (1 1 1) DMA #1 PIC #1 PIT Digital I/O - Kbd DMA Page PIC #2 DMA #2 FPU IOR IOW 0123456789101112131415 0000000001000011

46. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 46 Special Cycles Definition M/IO# = 0, D/C# = 0, W/R# = 1

47. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 47 Special Cycles Definition l Halt Cycle: CPU waits for INTR, NMI, Reset, or INIT. n Generated when Pentium executes a HLT instruction. n If interrupts are enabled, an INTR (e.g Timer Tick) will force the microprocessor out of a halt. l Shutdown Cycle: CPU waits for NMI, Reset, or INIT. n Generated by the Pentium: 3 Triple Fault: The CPU detects a further exception (e.g. General Protection Fault, Invalid Op Code, Stack Overflow) while executing the Double Fault Exception handler. 3 Internal Parity Error detected by the CPU. n Shutdown is decoded by the system board and generates a soft reset (INIT to Pentium) in a PC.

48. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 48 CPU Bus Cycles l A BUS CYCLE begins with the Processor driving an address and status (Control signals) and asserting ADS#. l A BUS CYCLE ends when the last BRDY# is returned to the Processor. l A BUS CYCLE may have 1 or 4 data transfers. n A SINGLE Cycle transfer is 64 bits maximum [8 bytes]. 3 The shortest cycle is 2 clocks n A BURST Cycle transfer is 256 bits (4*64) [32 bytes]

49. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 49 Microprocessor Single Bus Cycle

50. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 50 Basic Burst Read Cycle

51. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 51 Basic Burst Cycle l Burst Cycles can transfer larger quantities of data in fewer clocks than single transfer cycles. n e.g. - Single Cycle: 8 bytes (64 bits) in 2 clocks. 3 4 Singles cycles = 32 bytes in 8 clocks. n e.g. - Burst Cycle: 32 bytes (4*64 bits) in 5 clocks. l The Pentium uses burst mode for: n Cacheable read cycles n Write-back cycles when writing back a cache line. l Burst cycles are limited to an address area that begins at a 32-byte limit and the system board must calculate the other 3 burst addresses.

52. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 52 l The system board must generate the subsequent addresses(2nd, 3rd, 4th) in the following sequence. l Address Output by Pentium 1st 2nd3rd4th 00H08H10H18H 08H00H18H10H 10H 18H00H08H 18H10H08H00H l This is required in order to fill the Pentium 32t (20H) byte cache on 32 byte boundaries. n e.g. 32 bytes for addresses 100H - 11FH 3 100H, 108H, 110H, 118H; or 110H, 118H, 100H, 108H, etc Basic Burst Cycle

53. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 53 Basic Burst Cycle l These addresses can be generated as follows: l A3 toggles for every address; A4 toggles every OTHER address A7 6 5 4 3 2 1 A0 Address Output by Pentium 0 0 0 0 0 0 0 0 00H08H10H18H 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 A7 6 5 4 3 2 1 A0 Address Output by Pentium 0 0 0 0 1 0 0 0 08H00H18H10H 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0

54. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 54 Pentium™ Signal Description

55. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 55 Pentium™ Signal Description l This overview will describe the signals of the Pentium as used in a typical Single Processor PC system. n Multiprocessor support signals and MESI protocol signals are beyond the scope of this course.

56. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 56 Signal Description Clock Initialization Address Bus Address Mask Data Bus Address Parity Data Parity Bus Cycles Definition Bus Control Cache Control Cache Snooping Cache Flush Bus Arbitration Interrupts FP Error Reporting SMM Probe Mode TAP Port Internal Parity Error Pentium™ See the Pentium Data Book Hardware Interface section for a complete description of all signals.

57. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 57 Signal Description l CLOCK n CLK - Clock (Input) 3 Fundamental Timing for the Pentium 3 The CPU uses this signal as the internal processor clock. n BF - Bus Frequency (Input) 3 Bus Frequency determines the bus-to-core frequency ratio 3 When BF is strapped to Vcc, the processor will operate at a 2 to 3 bus to core frequency ratio. 3 When BF is strapped to Vss, the processor will operate at a 1 to 2 bus to core frequency ratio. 3 What symptoms might be exhibited if this signal is incorrect?

58. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 58 l Initialization n RESET - (Input) 3 Forces the CPU to begin execution at a known state. n INIT - Initialization (Input) 3 The Pentium processor initialization input pin forces the Pentium processor to begin execution in a known state. 3 The processor state after INIT is the same as the state after RESET except that the internal caches, write buffers, and floating point registers retain the values they had prior to INIT. Signal Description

59. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 59 l Address Bus n A31:A3 - ADDRESS bus lines 3 Output except for cache snooping n The number of address lines determines the amount of memory supported by the processor. n Determines where in the 4GB memory space or 64K IO space the processor is accessing. n These are input lines when AHOLD & EADS# are active for Inquire Cycles (snooping) Signal Description

60. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 60 Signal Description l Address Bus n BE7#:BEO#: Byte Enable lines (Outputs) n Byte Enables to enable each of the 8 bytes in the 64-bit data path. 3 Helps define the physical area of memory or I/O accessed. 3 The Pentium uses Byte Enables to address locations within a QWORD. 3 In effect a decode of the address lines A2-A0 which the Pentium does not generate. 3 Which lines go active depends on the address, and whether a byte, word, double word or quad word is required.

61. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 61 Signal Description l Address Mask n A20M#: Address 20 Mask (Input) 3 Emulates the address wraparound at 1 MByte which occurs on the 8086. 3 When A20M# is asserted, the Pentium processor masks physical address bit 20 (A20) before performing a lookup to the internal caches or driving a memory cycle on the bus. 3 A20#M must be asserted only when the processor is in real mode. l Internal Parity n IERR# - Internal Error (Output) 3 Alerts System of Internal Parity Errors

62. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 62 l Address Parity n AP Address Parity (I/O) 3 Bi-directional address parity pin for the address lines. 3 Address Parity is driven by the Pentium processor with even parity information on all CPU generated cycles in the same clock that the address is driven 3 Even parity must be driven back to the CPU during inquire cycles on this pin in the same clock as EADS#. 3 Not supported on all systems n APCHK#: Address Parity Check Signal (Output) 3 The status of the address parity check is driven on the APCHK# output. 3 Even Parity Checking Signal Description

63. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 63 Signal Description l Data Bus. n D63:DO - Data Lines (I/O). 3 The bi-directional 64-bit data path to or from the CPU. 3 The signal W/R# distinguishes direction. 3 During reads, the CPU samples the data bus when BRDY# is asserted. n DP7: DP0 - Data Parity (I/O) 3 Bi-directional data parity pins for the data bus. 3 Even Parity Check. One for each byte of the data bus 3 Output on writes, Input on reads. 3 Not supported on all systems.

64. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 64 l Bus Control n ADS# - Address Strobe (output) 3 Indicates that a new valid bus cycle is currently being driven by the Pentium processor. 3 The following are some of the signals which are valid when ADS#=0 »Addresses (A31:3) »Byte Enables (BE7#:0#) »Bus Cycle definition (M/IO#; D/C#; W/R#, CACHE#) 3 From power-on the ADS# signal should be asserted periodically when bus cycles are running. Signal Description

65. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 65 Signal Description l Bus Control (Cont.) n BRDY# - Burst Ready (Input) 3 Transfer complete indication. 3 The burst ready input indicates that the external system has presented data on the data pins in response to a read or that the external system has accepted the Pentium processor data in response to a write request. 3 This signal ends the current bus cycle and is used to extend bus cycles to allow slow devices extra time. 3 If LOW (non-burst cycles), this signal ends the current bus cycle and the next bus cycle can begin. 3 If HIGH the Pentium is prevented from continuing processing and wait states are added.

66. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 66 Signal Description l Bus Cycle Definition n M/IO# - Memory or Input/Output (output) 3 M/IO# distinguishes between Memory and I/O cycles. 3 The memory/input-output is one of the primary bus cycle definition pins. »1 = Memory Cycle »0 = Input/Output Cycle 3 It is driven valid in the same clock as the ADS# signal is asserted.

67. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 67 Signal Description l Bus Cycle Definition (Cont.) n D/C# - Data or Code (output) 3 D/C# distinguishes between data and code or special cycles (control) 3 The data/code output is one of the primary bus cycle definition pins. »1 = Data »0 = Code / Control »Control for Interrupt Acknowledge or Special Cycles 3 It is driven valid in the same clock as the ADS# signal is asserted.

68. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 68 Signal Description l Bus Cycle Definition (Cont.) n W/R# - Write or Read (output) 3 W/R# distinguishes between Write and Read cycles. 3 Write/read is one of the primary bus cycle definition pins. 3 1 = Write 3 0 = Read 3 It is driven valid in the same clock as the ADS# signal is asserted.

69. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 69 l Bus Cycle Definition (Cont.) n Cache# - Cacheability (output) 3 Processor indication of internal cacheability. 3 The L1 cache must be enabled using the CD bit in CR0 for Cache# to be asserted low. 3 The Cache# signal could also be described as the BURST instruction signal, because the Cache# signal (qualified with KEN#) results in a burst mode transfer of 32 bytes of code or data. 3 Cache# and Ken# are used together to determine if a read will be turned into a linefill. (Burst cycle). 3 During write-back cycles, the CPU asserts the CACHE# signal (KEN# does not have to be asserted) Signal Description

70. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 70 l Bus Cycle Definition (Cont.) n NA# - Next Address (Input) 3 Indicates external memory is prepared for a pipeline cycle. 3 An active next address input indicates that the external memory system is ready to accept a new bus cycle although all data transfers for the current cycle have not yet completed. 3 When NA# is asserted, the Pentium supplies the address for the start of the next transfer early, so that the memory system can latch the new address before the transfer is ready to start. 3 A detailed discussion of Address Pipelining is beyond the scope of this course. Signal Description

71. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 71 Signal Description l Bus Cycle Definition (Cont.) n Lock# - Bus Lock (Output) 3 The bus lock pin indicates that the current bus cycle is locked, typically for a read-modify-write operation. 3 The CPU will not allow a bus hold when LOCK# is asserted. 3 Locked cycles are generated when the programmer prefixes certain instructions with the LOCK prefix. »e.g. LOCK INC [EDI];Increment a memory location 3 Locked cycles are generated automatically for certain bus transfer operations. »Interrupt Acknowledge cycles »The XCHG instructions when 1 operand is memory-based. »See Pentium manual for more details.

72. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 72 Signal Description l Cache Control n KEN# - Cache Enable (Input) 3 Indicates to the Pentium whether or not the system can support a cache line fill for the current cycle. 3 Cache# and Ken# are used together to determine if a read will be turned into a linefill. (Burst cycle). n WB/WT# - Write-back/Write-through (Input) 3 This pin allows a cache line to be defined as a a write back or write-through on a line by line basis. 3 This signal is necessary for the implementation of the MESI protocol. 3 Detailed discussion of the MESI protocol is beyond the scope of this course.

73. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 73 Signal Description l Cache Snooping n AHOLD - Address Hold (Input) 3 Floats the address bus so an inquire cycle can be driven to the Pentium. 3 AHOLD allows another bus master (e.g. DMA ctlr) to drive the CPU address bus with the address for an inquire cycle. »Effectively changes address lines to inputs. 3 All other signals remain active so data for previously sent bus cycles can still be transferred. n EADS# - External Address Strobe (Input) 3 Indicates that a valid external address has been driven onto the CPU address pins for a snoop inquire cycle. 3 Recognized while AHOLD is asserted.

74. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 74 l Cache Snooping (Cont.) n HIT# - On Chip Cache hit (Output) 3 Inquire Cycle Hit/Miss Indication 3 Externally indicates whether an inquire cycle resulted in a hit or miss. n HITM# - On Chip Cache Hit Modified (Output) 3 Hit/Miss to a modified line 3 Externally indicates whether an inquire cycle hit a modified line in the data cache. 3 HITM# is never asserted without HIT# also being asserted Signal Description

75. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 75 l Cache Flush n Flush# - Cache Flush (Input) 3 Writes all modified lines in the data cache back and flushes the code and data caches. 3 A Flush Acknowledge special cycle will be generated by the Pentium™ indicating completion of the invalidation and writeback. Signal Description

76. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 76 Signal Description l Bus Arbitration n HOLD - Bus Hold (Input) 3 Allows another bus master complete control of the CPU bus. 3 In response to the bus hold request, the Pentium processor will float most of its output and input/output pins and assert HLDA after completing all outstanding bus cycles. 3 The Pentium processor will maintain its bus in this state until HOLD is de-asserted. n HLDA - Bus Hold Acknowledge (Output) 3 External indication that the Pentium™ outputs are floated.

77. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 77 Signal Description l Bus Arbitration (Cont.) n BOFF# - Backoff (Input) 3 Forces the Pentium to get off the bus in the next clock. 3 After BOFF# is removed, the Pentium restarts the bus cycle. n BREQ - Bus Request (output) 3 Indicates externally when a bus cycle is pending internally. 3 Used to inform the arbitration logic that the Pentium need control of the bus to perform a bus cycle.

78. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 78 Signal Description l Interrupts n INTR - Maskable Interrupt (Input) 3 Indicates that an external interrupt has been generated. 3 If the IF(Interrupt Enable Flag) bit in the EFLAGS register is set, the Pentium processor will generate two locked interrupt acknowledge bus cycles (to get type number) and vectors to an interrupt handler after the current instruction execution is completed. n NMI - Non-Maskable Interrupt (Input) 3 Indicates that an external non maskable interrupt has been generated. 3 The Pentium processor will vector to a Type 2 interrupt handler after the current instruction execution is completed.

79. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 79 l Floating Point Error Reporting n FERR# - Floating Point Error (Output) 3 FERR# is included for compatibility with systems using DOS-type floating point error reporting (IRQ13) 3 Indicates that an unmasked error occurred 3 FERR# is similar to the ERROR# pin on the Intel387 TM math coprocessor. n IGNNE# - Ignore Numeric Exception (Input) 3 Indicates ignore numeric exception. 3 Valid only when CR0 NE bit is reset. 3 Permits processor to continue execution before the floating point interrupt service routine has cleared the error. Signal Description

80. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 80 Signal Description l System Management Mode n SMI# - System Management Mode Interrupt (Input) 3 Latches a System Management Interrupt Request 3 When the latched SMI# is recognized on an instruction boundary, the processor enters System Management Mode n SMIACT# - Sys Mgt Interrupt Active (Output) 3 Indicates that the processor is operating in SMM.

81. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 81 l Test Access Port (TAP) 3 Signals for Hardware Debug Support (ITP) & Boundary Scan Testing. n TCK - Testability Clock Input (Input) 3 The testability clock input provides the clocking function for the Pentium processor boundary scan in accordance with the IEEE Boundary Scan interface. n TMS - Test Mode Select (Input) 3 The value of the test mode select input signal sampled at the rising edge of TCK controls the sequence of TAP controller state changes. Signal Description

82. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 82 Signal Description l Test Access Port (TAP) (Cont.) n TDI - Test Data Input (Input) 3 The test data input is a serial input for the test logic. 3 TAP instructions and data are shifted into the Pentium processor on the TDI pin on the rising edge of TCK when the TAP controller is in an appropriate state. n TDO - Test Data Output (Output) 3 The test data output is a serial output of the test logic. 3 TAP instructions and data are shifted out of the Pentium processor on the TDO pin on TCK’s falling edge when the TAP controller is in the appropriate state.

83. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 83 Signal Description l Test Access Port (TAP) (Cont.) n TRST# - Test Reset (Input) 3 When asserted, the test reset input allows the TAP controller to be asynchronously initialized l Probe Mode n R/S# - Resume/Stop [Run/Scan] (Input) 3 The run/stop input is an asynchronous, edge-sensitive interrupt used to stop the normal execution of the processor and place it into an idle state. n PRDY - Probe Ready (Output) 3 The probe ready output pin indicates that the processor has stopped normal execution in response to the R/S# pin going active. The CPU enters Probe Mode.

84. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 84 Pentium™ Address/Data Bus Exercise

85. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 85 Pentium Address/Data Bus Exercise Assume you used an ITP debug tool to write the following into memory. n Write 55H to 8 bytes @ 0:0 (0H-7H Physical) n Write AAH to 8 bytes @ 0:8 (8H-0FH Physical) 3 NOTE: Or vice versa (Address not significant) Result after reading the memory written to above! 0x000000000000P 55 55 55 55 55 5d 55 55 'UUUUU]UU' 0x000000000008P aa aa aa aa aa ba aa aa '........' l Using your knowledge of Pentium address & byte enable generation, determine what Data Bus problem could cause the bad data? Hint: D63.....................................D0 55 55 5d 55 55 55 55 55

86. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 86 Where to get more information l Pentium™ Processor User’s Manual n Order Number 241428 l Pentium™ Architecture & Programming Manual n Order Number 241430 l Pentium™ Processor System Architecture n Mindshare (ISBN 1-881609-07-3) l The Indispensable Pentium™ Book n Addison-Wesley (ISBN 0-201-87727-9)

87. Rev. 1.0 Sys MFG T/ED 7/13/2015 PC Architecture For Technicians Level-1 Technical Excellence Development Series Ch 10 - Page 87 SUMMARY WE HAVE DISCUSSED THE FOLLOWING: l The basic architecture of the Pentium processor. l The use of the Pentium Registers. l The various Pentium buses. l The use of the Byte Enables. l Pentium address generation. l Pentium Bus Cycle Definitions. l Pentium Single & Burst cycles. l Pentium Signal Descriptions.