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Chapter 2 (cont.) An Introduction to the 80x86 Microprocessor Family Objectives: The different addressing modes and instruction types available The usefulness.

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Presentation on theme: "Chapter 2 (cont.) An Introduction to the 80x86 Microprocessor Family Objectives: The different addressing modes and instruction types available The usefulness."— Presentation transcript:

1 Chapter 2 (cont.) An Introduction to the 80x86 Microprocessor Family Objectives: The different addressing modes and instruction types available The usefulness of interrupts Some of the differences between the 8086 and the 80286, 80386, and Pentium microprocessors EE314 Microprocessor Systems Based on "An Introduction to the Intel Family of Microprocessors" by James L. Antonakos

2 2.7 Addressing modes F0000 E0000 D0000 C0000 B0000 A FFFFF Real-Mode Addressing space The addressing space of the processor in the real mode: 20 address bits used 1Mbyte wide address to FFFFF Logically Byte organized A particular way to split memory in segments: non-overlapping A segment is a 64KB memory block, beginning at a multiple-of-16 (10H) address Overlapping segments Superposed segments The segment 38130H-4812FH The content of the used segment register is 3813H. Interrupt pointer table 003FF Reset instruction area FFFFF FFFF0

3 MOV CL,[ BP - 4] 2.7 Addressing modes Specify the operand to be used. To generate an address, a segment register is used also. Immediate addressing: the operand is a number included in the instruction body. MOV CX,1024 Register addressing: the operand is a register. ADD AL, BL Direct addressing: the operand address is a number in [] or the value of a symbol (no [].) MOV AX,[3000] MOV BL,COUNTER Register indirect addressing: the register enclosed in [ ] specifies the operand address. MOV BX,[SI] Indexed addressing: the operand address is the sum of the value of the index register and a number, both enclosed in [ ]. MOV BX,[ SI + 10] Based addressing: is similar to indexed, but using BP (base pointer) register. Based-indexed addressing: the operand address is the sum of the values of BP and one of the index registers (SI or DI). MOV DS:[ BP + DI],AX Based-indexed with displacement addressing: ads to the former an offset value. MOV DL,[ BP][ DI + 2] or MOV DL,[ BP + DI + 2] Port addressing: used by input/output instructions. The address of the source port for IN or destination port for OUT is a number or a register content. OUT 80H, AL IN AL, DX The displacement is a signed 2’s complement byte or word Segment overriding

4 2.7 Addressing modes 32-Bit Addressing Mode Base register EAX EBX ECX EDX EBP ESI EDI ESP + Segment register CS DS ES FS GS SS Scale factor Displacement none 8-bit 32-bit + Index register EAX EBX ECX EDX EBP ESI EDI * + Effective address Ex: MOV EAX,[EBX][ECX*4+6] 0010 B4 09MOVAH, D RLEADX, TABLE 0016 CD 21INT21H 0018 B4 09MOVAH, 9 001A 66 8D 1E 0000 RLEAEBX, TABLE 001F 66 BA MOVEDX, D 14 93LEADX, [EBX][EDX*4] 0029 CD 21INT21H Prefixes to allow using 32-bit registers in real mode

5 2.8 Interrupts Hardware and Software Interrupts The nonmaskable interrupt is generated by en external device, via the NMI pin. Cannot be ignored by the microprocessor. The maskable interrupts (0…FFH) can be generated by: an external device, via the INTR pin (the external device has to specify the interrupt number). (IF (interrupt flag) in FLAGS register enables or disables the  P to accept maskable interrupts.) microprocessor itself (i.e. when trying to divide by 0), (the interrupt number is hardware defined). Software interrupts using the INT instruction (followed by the interrupt number). The Interrupt Vector Table (or Interrupt Pointer Table) The memory block from address to 003FF. There are 1024 bytes, each of the 256 maskable interrupts uses four bytes to store the address where the corresponding ISR (Interrupt Service Routine) begins. The ISR address for interrupt number xx is stored beginning at address xx*4, in form CS:IP. From low to high address, the bytes are stored in the order: IP low, IP high, CS low and CS high (byte swapping). Example: The pointer for INT 21 is located at address:21H*4=84H. C> debug -d 0:80 L : B f 03 FB 0A 8A 03 FB 0A -q CS=0726H IP=16B4H INT 21 ISR: 08914H Hardware interrupts

6 2.9 The 8086: the first 80x86 Machine 8088 and 8086 pin assignments GND A14 A13 A12 A11 A10 A9 A8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND Vcc A15 A16/S3 A17/S4 A18/S5 A19/S6 ___ SS0(HIGH) ___ MN/MX ___ RD ___ ____ HOLD(RQ/GT0) ___ ____ HLDA (RQ/GT1) ___ ______ WR(LOCK) __ __ IO/M(S2) __ __ DT/R(SI) ____ __ DEN(S0) ALE(QS0) _____ INTA(QS1) _____ TEST READY RESET GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND Vcc AD15 A16/S3 A17/S4 A18/S5 A19/S6 ____ BHE/S7 ___ MN/MX ___ RD ___ ____ HOLD(RQ/GT0) ___ ____ HLDA (RQ/GT1) ___ ______ WR(LOCK) __ __ IO/M(S2) __ __ DT/R(SI) ____ __ DEN(S0) ALE(QS0) _____ INTA(QS1) _____ TEST READY RESET

7 2.9 The 8086: the first 80x86 Machine


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